Memory-flow control register
Described apparatuses and methods relate to a memory-flow control register for a memory system that may support a nondeterministic protocol. To help manage the flow of memory requests in a system, a memory device can include logic, such as a hardware register, that can store values indicative of a total number of memory requests that are serviceable by the memory device at a time. The logic can be configured by device manufacturers during assembly. The manufacturers can determine the limits or capabilities of the system, based on the components and structures, and publish the capabilities, including QoS, based on the limits. When the memory device is connected to a host, the host can read the values and limit the number of memory requests sent to the device based on the values. Accordingly, the memory-flow control register can improve latency and bandwidth in accessing a memory device over an interconnect.
1. A method comprising:
transmitting, by a controller, a request to read one or more values indicative of a number of memory requests serviceable by a Compute Express Link (CXL) memory device, the one or more values stored in at least one register mapped to a CXL device configuration space of the CXL memory device, the at least one register including one or more of:
a first register that includes at least a first value indicative of a total combined number of write requests and read requests that can be outstanding in or at the CXL memory device;
a second register that includes at least a second value indicative of a number of write requests that can be outstanding in or at the CXL memory device; or
a third register that includes at least a third value indicative of a number of read requests that can be outstanding in or at the CXL memory device; and
receiving, by the controller, a response from the CXL memory device, the response including at least a portion of the one or more values.
2. The method of claim 1 , further comprising:
controlling a quantity of memory requests outstanding in the CXL memory device based on the one or more values.
3. The method of claim 1 , further comprising:
controlling a quantity of memory requests outstanding in the CXL memory device to prevent the quantity of memory requests outstanding in the CXL memory device from exceeding the number of memory requests indicated by the one or more values.
4. The method of claim 1 , further comprising:
controlling a quantity of memory requests outstanding in the CXL memory device to prevent the quantity of memory requests outstanding in the CXL memory device from exceeding the number of memory requests indicated by the one or more values, during a period in which the controller is operating under a credit-based flow control system that indicates one or more credits are available to allow the controller to transmit memory requests to the CXL memory device.
5. The method of claim 1 , further comprising:
comparing, by the controller, a quantity of memory requests outstanding in the CXL memory device to the number of memory requests serviceable by the CXL memory device using the one or more values; and
transmitting a memory request to the CXL memory device responsive to the quantity of memory requests outstanding in the CXL memory device being less than the number of memory requests serviceable by the CXL memory device.
6. The method of claim 1 , further comprising:
comparing, by the controller, a quantity of memory requests outstanding in the CXL memory device to the number of memory requests serviceable by the CXL memory device using the one or more values; and
ceasing to transmit memory requests to the CXL memory device responsive to the quantity of memory requests outstanding in the CXL memory device being greater than or equal to the number of memory requests serviceable by the CXL memory device.
7. The method of claim 1 , further comprising:
reading, by the controller, the one or more values stored in the at least one register of the CXL memory device during an initialization operation.
8. The method of claim 7 , wherein the initialization operation is responsive to at least one of:
the CXL memory device powering up; or
the CXL memory device being connected to the controller or a device associated with the controller.
9. The method of claim 1 , wherein the one or more values indicative of the number of memory requests serviceable by the CXL memory device comprise at least one of:
the first value;
the first value and the second value;
the first value and the third value; or
the second value and the third value.
10. The method of claim 1 , wherein the CXL memory device comprises a Type 1 CXL device, a Type 2 CXL device, or a Type 3 CXL device.
11. The method of claim 1 , wherein the controller comprises a CXL controller.
12. A method comprising:
receiving, at a Compute Express Link (CXL) memory device, a request to read one or more values indicative of a number of memory requests serviceable by the CXL memory device, the one or more values read from at least one register mapped to a CXL device configuration space of the CXL memory device, the at least one register including one or more of:
a first register that includes at least a first value indicative of a total combined number of write requests and read requests that can be outstanding in or at the CXL memory device;
a second register that includes at least a second value indicative of a number of write requests that can be outstanding in or at the CXL memory device; or
a third register that includes at least a third value indicative of a number of read requests that can be outstanding in or at the CXL memory device; and
transmitting, by the CXL memory device, a response including at least a portion of the one or more values.
13. The method of claim 12 , wherein the one or more values indicative of the number of memory requests serviceable by the CXL memory device comprise at least one of:
the first value;
the first value and the second value;
the first value and the third value; or
the second value and the third value.
14. The method of claim 12 , wherein the CXL memory device comprises a Type 1 CXL device, a Type 2 CXL device, or a Type 3 CXL device.
15. An apparatus comprising:
an interface configured to couple to a Compute Express Link (CXL) memory device via an interconnect; and
a controller coupled to the interface, the controller configured to:
transmit, via the interconnect, a request to the CXL memory device to read one or more values indicative of a number of memory requests serviceable by the CXL memory device, the one or more values stored in at least one register mapped to a CXL device configuration space of the CXL memory device, the at least one register including one or more of:
a first register that includes at least a first value indicative of a total combined number of write requests and read requests that can be outstanding in or at the CXL memory device;
a second register that includes at least a second value indicative of a number of write requests that can be outstanding in or at the CXL memory device; or
a third register that includes at least a third value indicative of a number of read requests that can be outstanding in or at the CXL memory device; and
receive, via the interconnect, a response from the CXL memory device, the response including at least a portion of the one or more values.
16. The apparatus of claim 15 , wherein the controller is further configured to:
control a quantity of memory requests outstanding in the CXL memory device based on the one or more values.
17. The apparatus of claim 15 , wherein the controller is further configured to:
control a quantity of memory requests outstanding in the CXL memory device to prevent the quantity of memory requests outstanding in the CXL memory device from exceeding the number of memory requests indicated by the one or more values.
18. The apparatus of claim 15 , wherein the controller is further configured to:
control a quantity of memory requests outstanding in the CXL memory device to prevent the quantity of memory requests outstanding in the CXL memory device from exceeding the number of memory requests indicated by the one or more values, the control occurring during a period in which the controller is operating under a credit-based flow control system that indicates one or more credits are available to allow the controller to transmit memory requests to the CXL memory device.
19. The apparatus of claim 15 , wherein the controller is further configured to:
compare a quantity of memory requests outstanding in the CXL memory device to the number of memory requests serviceable by the CXL memory device using the one or more values; and
transmit a memory request to the CXL memory device responsive to the quantity of memory requests outstanding in the CXL memory device being less than the number of memory requests serviceable by the CXL memory device.
20. The apparatus of claim 15 , wherein the controller is further configured to:
compare a quantity of memory requests outstanding in the CXL memory device to the number of memory requests serviceable by the CXL memory device using the one or more values; and
cease to transmit memory requests to the CXL memory device responsive to the quantity of memory requests outstanding in the CXL memory device being greater than or equal to the number of memory requests serviceable by the CXL memory device.
21. The apparatus of claim 15 , wherein the controller is further configured to:
transmit, via the interconnect, the request to the CXL memory device to read the one or more values stored in the at least one register of the CXL memory device during an initialization operation.
22. The apparatus of claim 21 , wherein the initialization operation is responsive to at least one of:
the CXL memory device powering up; or
the CXL memory device being connected to the controller or a device associated with the controller.
23. The apparatus of claim 15 , wherein the one or more values indicative of the number of memory requests serviceable by the CXL memory device comprise at least one of:
the first value;
the first value and the second value;
the first value and the third value; or
the second value and the third value.
24. The apparatus of claim 15 , wherein the interconnect is configured to comport with at least one CXL standard.
25. The apparatus of claim 15 , wherein the controller comprises a CXL controller.
26. An apparatus comprising:
an interface configured to couple to a host device via an interconnect; and
at least one register that is:
configured to:
be readable by the host device via the interconnect; and
store one or more values, the one or more values indicative of a number of memory requests serviceable by a Compute Express Link (CXL) memory device associated with the apparatus; and
mapped to a CXL device configuration space of the CXL memory device associated with the apparatus, the at least one register including one or more of:
a first register that includes at least a first value indicative of a total combined number of write requests and read requests that can be outstanding in or at the CXL memory device;
a second register that includes at least a second value indicative of a number of write requests that can be outstanding in or at the CXL memory device; or
a third register that includes at least a third value indicative of a number of read requests that can be outstanding in or at the CXL memory device.
27. The apparatus of claim 26 , wherein the one or more values indicative of the number of memory requests serviceable by the CXL memory device comprise at least one of:
the first value;
the first value and the second value;
the first value and the third value; or
the second value and the third value.
28. The apparatus of claim 26 , wherein the interconnect is configured to comport with at least one CXL standard.
29. The apparatus of claim 26 , wherein the CXL memory device comprises a Type 1 CXL device, a Type 2 CXL device, or a Type 3 CXL device.
30. The apparatus of claim 26 , wherein write and read memory requests that can be outstanding in or at the CXL memory device comprise one or more of:
write memory requests or read memory requests that are pending or extant in or at the CXL memory device;
write memory requests or read memory requests that have been received at the CXL memory device but not processed by the CXL memory device;
write memory requests or read memory requests that have been received by the CXL memory device but not yes responded to by the CXL memory device; or
write memory requests or read memory requests that are in-progress in downstream or backend components of the CXL memory device.
31. The method of claim 1 , wherein write and read memory requests that can be outstanding in or at the CXL memory device comprise one or more of:
write memory requests or read memory requests that are pending or extant in or at the CXL memory device;
write memory requests or read memory requests that have been received at the CXL memory device but not processed by the CXL memory device;
write memory requests or read memory requests that have been received by the CXL memory device but not yes responded to by the CXL memory device; or
write memory requests or read memory requests that are in-progress in downstream or backend components of the CXL memory device.
32. The method of claim 1 , wherein the at least one register mapped to the CXL device configuration space of the CXL memory device is:
separate from the controller; or
integrated with the controller.
33. The method of claim 12 , wherein write and read memory requests that can be outstanding in or at the CXL memory device comprise one or more of:
write memory requests or read memory requests that are pending or extant in or at the CXL memory device;
write memory requests or read memory requests that have been received at the CXL memory device but not processed by the CXL memory device;
write memory requests or read memory requests that have been received by the CXL memory device but not yes responded to by the CXL memory device; or
write memory requests or read memory requests that are in-progress in downstream or backend components of the CXL memory device.
34. The apparatus of claim 15 wherein write and read memory requests that can be outstanding in or at the CXL memory device comprise one or more of:
write memory requests or read memory requests that are pending or extant in or at the CXL memory device;
write memory requests or read memory requests that have been received at the CXL memory device but not processed by the CXL memory device;
write memory requests or read memory requests that have been received by the CXL memory device but not yes responded to by the CXL memory device; or
write memory requests or read memory requests that are in-progress in downstream or backend components of the CXL memory device.
35. The apparatus of claim 15 , wherein the at least one register mapped to the CXL device configuration space of the CXL memory device is:
separate from the controller; or
integrated with the controller.
36. The apparatus of claim 15 , wherein the controller determines the number of memory requests that are serviceable by the CXL memory device based on a quantity of memory requests that are serviceable by the CXL memory device while providing a specified performance parameter defined by a quality of service (QoS) parameter.