Tagged memory operated at lower vmin in error tolerant system

1. A method, comprising:

determining a first operational accuracy of a first subset of memory cells of a memory array, which, in operation, store data, wherein the memory array is arranged as a plurality of rows of memory cells intersecting a plurality of columns of memory cells;

determining a second operational accuracy of a second subset of memory cells of the memory array, which, in operation, store data, wherein the second operational accuracy is higher than the first operational accuracy;

receiving a request to perform computing operations;

determining an operation type of the computing operations to be performed;

in response to a first determined operation type, performing the computing operations using the first subset of memory cells, wherein performing the computing operations using the first subset of memory cells includes providing a first operational voltage to the first subset of memory cells that is lower than a second operational voltage provided to the second subset of memory cells; and

in response to a second determined operation type, performing the computing operations using the second subset of memory cells.

2. The method of claim 1 , wherein performing the computing operations using the second subset of memory cells includes:

providing the second operational voltage to the second subset of memory cells that is higher than the first operational voltage provided to the first subset of memory cells.

3. The method of claim 1 , comprising:

in response to receiving a first request to perform first computing operations of the first determined operation type, performing the first computing operations using the first subset of memory cells at the first operational voltage; and

in response to receiving a second request to perform second computing operations of the second determined operation type based on a result of the performance of the first computing operations, performing the second computing operations using the second subset of memory cells at the second operational voltage that is higher than the first operational voltage.

4. The method of claim 1 , wherein determining the operation type of the computing operations to be performed includes:

identifying an acceptable operational accuracy of a result of performing the computing operations;

in response to the acceptable operational accuracy being below a threshold value, selecting the first determined operation type to use the first subset of memory cells at the first operational voltage; and

in response to the acceptable operational accuracy being above the threshold value, selecting the second determined operational type to use the second subset of memory cells at the second operational voltage that is greater than the first operational voltage.

5. The method of claim 1 , wherein first subset of memory cells consists of a subset of columns of the plurality of columns of cells, a subset of rows of the plurality of rows of cells, or both a subset of columns of the plurality of columns of cells and a subset of rows of the plurality of rows of cells.

6. A non-transitory computer-readable medium having contents which cause a computing device to perform a method, the method comprising:

determining a first operational accuracy of a first subset of memory cells of a memory array of the computing device, wherein the memory cells of the memory array, in operation, store data, and the memory array is arranged as a plurality of rows of memory cells intersecting a plurality of columns of memory cells;

determining a second operational accuracy of a second subset of memory cells of the memory array, wherein the second operational accuracy is higher than the first operational accuracy;

receiving a request to perform computing operations;

determining an operation type of the computing operations to be performed;

in response to a first determined operation type, performing the computing operations using the first subset of memory cells, wherein performing the computing operations using the first subset of memory cells includes providing a first operational voltage to the first subset of memory cells that is lower than a second operational voltage provided to the second subset of memory cells; and

in response to a second determined operation type, performing the computing operations using the second subset of memory cells.

7. The non-transitory computer-readable medium of claim 6 , wherein determining the operation type of the computing operations to be performed includes:

identifying an acceptable operational accuracy of a result of performing the computing operations;

in response to the acceptable operational accuracy being below a threshold value, selecting the first determined operational type to use the first subset of memory cells at the first operational voltage; and

in response to the acceptable operational accuracy being above the threshold value, selecting the second determined operational type to use the second subset of memory cells at the second operational voltage that is greater than the first operational voltage.

8. The non-transitory computer-readable medium of claim 6 , wherein the contents comprise instructions executed by the computing device.

9. A device, comprising:

a memory array arranged as a plurality of rows of memory cells intersecting a plurality of columns of memory cells, wherein the memory cells, in operation, store data; and

processing circuitry coupled to the memory array, wherein the processing circuitry, in operation:

determines a first operational accuracy of a first subset of memory cells of the memory array;

determines a second operational accuracy of a second subset of memory cells of the memory array, wherein the second operational accuracy is higher than the first operation accuracy;

determines an operation type of computing operations associated with a received request to perform computing operations;

in response to determining a first operation type, performs the computing operations using the first subset of memory cells, wherein performing the computing operations using the first subset of memory cells includes providing a first operational voltage to the first subset of memory cells that is lower than a second operational voltage provided to the second subset of memory cells; and

in response to determining a second operation type, performs the computing operations using the second subset of memory cells.

10. The device of claim 9 , wherein performing the computing operations using the second subset of memory cells includes:

providing the second operational voltage to the second subset of memory cells that is higher than the first operational voltage provided to the first subset of memory cells.

11. The device of claim 9 , wherein the processing circuitry, in operation:

responds to receiving a first request to perform first computing operations of the first determined operation type by performing the first computing operations using the first subset of memory cells at the first operational voltage; and

responds to receiving a second request to perform second computing operations of the second determined operation type based on a result of the performance of the first computing operations by performing the second computing operations using the second subset of memory cells at the second operational voltage that is higher than the first operational voltage.

12. The device of claim 9 , wherein the processing circuitry, in operation:

identifies an acceptable operational accuracy of a result of performing the computing operations;

in response to the acceptable operational accuracy being below a threshold value, selects the first determined operation type to use the first subset of memory cells at the first operational voltage; and

in response to the acceptable operational accuracy being above the threshold value, selects the second determined operation type to use the second subset of memory cells at the second operational voltage that is greater than the first operational voltage.

13. The device of claim 9 , wherein the processing circuitry comprises:

memory management circuitry coupled to the plurality of memory cells; and

power control circuitry, coupled to the memory management circuitry and the plurality of memory cells.