Semiconductor package

1. A semiconductor package comprising:

a semiconductor chip;

a connection terminal; and

a redistribution substrate configured to electrically connect to the semiconductor chip via the connection terminal, the redistribution substrate including,

a pad pattern including a pad via and a pad on the pad via,

a first redistribution pattern including a first via and a first interconnection on the first via, and

a second redistribution pattern between the first redistribution pattern and the pad pattern, the second redistribution pattern including a second via and a second interconnection on the second via, the second interconnection having a recess region therein where a portion of a top surface of the second interconnection is recessed with a bottom surface of the recess region located at a lower level than a topmost surface of the second interconnection, the pad via filling a portion of the recess region such that a bottom surface of the pad via is higher than a bottom surface of the second interconnection in a direction perpendicular to the top surface of the second interconnection.

2. The semiconductor package of claim 1 , further comprising:

an external terminal on a bottom surface of the redistribution substrate; and

an under bump pattern in contact with a top surface of the external terminal and electrically connected to the first redistribution pattern.

3. The semiconductor package of claim 1 , wherein the redistribution substrate further comprises:

at least one insulating layer covering the first redistribution pattern and the second redistribution pattern, the at least one insulating layer including a photosensitive polymer.

4. The semiconductor package of claim 1 , wherein the redistribution substrate further comprises:

at least one fine pattern laterally spaced apart from the first redistribution pattern.

5. The semiconductor package of claim 1 , further comprising:

a pad seed pattern covering the bottom surface and an inner sidewall of the recess region.

6. The semiconductor package of claim 1 , further comprising:

a chip stack mounted on the redistribution substrate with the chip stack being laterally spaced apart from the semiconductor chip, the chip stack including a plurality of chips vertically stacked on the redistribution substrate.

7. The semiconductor package of claim 1 , further comprising:

an insulating layer covering the first redistribution pattern and the second redistribution pattern;

a first seed pattern between the insulating layer and a bottom surface of the first redistribution pattern; and

a second seed pattern between the insulating layer and a bottom surface of the second redistribution pattern.

8. The semiconductor package of claim 1 , wherein, in a direction parallel to the top surface of the redistribution substrate, widths of a top of the first via and a top of the second via are greater than widths of a bottom of the first via and a bottom of the second via, respectively.

9. The semiconductor package of claim 1 , wherein a thickness between the bottom surface of the recess region and the topmost surface of the second interconnection ranges from 1 μm to 5 μm.

10. The semiconductor package of claim 1 , wherein a width of the bottom surface of the recess region ranges from 5 μm to 15 μm.

11. A semiconductor package comprising:

a semiconductor chip;

a connection terminal;

a redistribution substrate configured to electrically connect to the semiconductor chip via the connection terminal, the redistribution substrate including,

an under bump pattern,

a first redistribution pattern on the under bump pattern,

a second redistribution pattern on the first redistribution pattern, the second redistribution pattern including a second via and a second interconnection on the second via, the second interconnection having a recess region therein where a portion of a top surface of the second interconnection is recessed,

at least one fine pattern on the under bump pattern and laterally spaced apart from the first redistribution pattern and the second redistribution pattern,

an insulating layer covering the first redistribution pattern, the second redistribution pattern and the at least one fine pattern,

a pad pattern including a pad via and a pad on the pad via, the pad via filling a portion of the recess region such that a bottom surface of the pad via is higher than a bottom surface of the second interconnection in a direction perpendicular to the top surface of the second interconnection, and

a pad seed pattern between the pad pattern and the insulating layer, the pad seed pattern covering an inner sidewall and a bottom surface of the recess region; and

an external terminal on a bottom surface of the redistribution substrate such that the external terminal contacts the under bump pattern.

12. The semiconductor package of claim 11 , further comprising:

a first seed pattern between the insulating layer and a bottom surface of the first redistribution pattern; and

a second seed pattern between a bottom surface of the second via and a top surface of the first redistribution pattern, between a sidewall of the second via and the insulating layer and between the bottom surface of the second interconnection and the insulating layer.

13. The semiconductor package of claim 11 , wherein, in a direction parallel to the top surface of the redistribution substrate, a width of a top of the pad via is greater than a width of a bottom of the pad via.

14. The semiconductor package of claim 11 , wherein the first redistribution pattern comprises:

a first via; and

a first interconnection on the first via.

15. The semiconductor package of claim 11 , further comprising:

a molding layer covering the top surface of the redistribution substrate and the semiconductor chip.

16. The semiconductor package of claim 11 , wherein the bottom surface of the recess region is at a lower level than a topmost surface of the second interconnection.