Method for selective removal of gate dielectric from dummy fin
View Patent ↗A method includes forming an active channel region, forming a dummy channel region, forming a first gate dielectric layer over the active channel region, forming a second gate dielectric layer over the dummy channel region, removing the second gate dielectric layer from the dummy channel region, forming a gate isolation region over and contacting the dummy channel region, and forming a first gate stack and a second gate stack. The first gate stack is on the active channel region. The gate isolation region separates the first gate stack from the second gate stack.
1. A method comprising:
forming an active channel region;
forming a dummy channel region;
forming a first gate dielectric layer over the active channel region;
forming a second gate dielectric layer over the dummy channel region;
removing the second gate dielectric layer from the dummy channel region;
after the second gate dielectric layer is removed, forming a dummy gate electrode over the dummy channel region;
patterning the dummy gate electrode to form an opening, wherein the dummy channel region is exposed through the opening;
forming a gate isolation region in the opening and contacting the dummy channel region; and
forming a first gate stack and a second gate stack, wherein the first gate stack is on the active channel region, and wherein the gate isolation region separates the first gate stack from the second gate stack.
2. The method of claim 1 further comprising, after the gate isolation region is formed, removing the dummy gate electrode.
3. The method of claim 1 , wherein the first gate stack and the second gate stack are in contact with, and are separated from each other by, both of the dummy channel region and the gate isolation region.
4. The method of claim 1 , wherein the first gate stack and the second gate stack comprise a first gate dielectric and a second gate dielectric, respectively, wherein each of the first gate dielectric and the second gate dielectric has a sidewall portion in physical contact with sidewalls of both of the dummy channel region and the gate isolation region.
5. The method of claim 1 , wherein the first gate dielectric layer and the second gate dielectric layer are deposited in a common deposition process.
6. The method of claim 1 further comprising:
removing the first gate dielectric layer from the active channel region; and
forming a replacement gate dielectric layer on the active channel region.
7. The method of claim 1 , wherein the dummy channel region comprises:
a first portion, wherein the second gate dielectric layer is removed from the first portion; and
a second portion, wherein the second gate dielectric layer remains on the second portion at a time after the second gate dielectric layer is removed from the first portion.
8. The method of claim 7 , where the first portion is between the first gate stack and the second gate stack, and the method further comprises forming a first source/drain region and a second source/drain region on opposing sides of the second portion.
9. A method comprising:
forming a dummy fin comprising a first portion and a second portion, wherein the dummy fin comprises a dielectric material;
forming a dummy gate dielectric on the dummy fin;
removing the dummy gate dielectric from the first portion of the dummy fin;
after the dummy gate dielectric is removed from the first portion of the dummy fin, forming a dummy gate electrode over the dummy fin;
patterning the dummy gate electrode to form an opening;
forming a gate isolation region in the opening and over the dummy fin, wherein a bottom surface of the gate isolation region contacts a first top surface of the first portion of the dummy fin to form an interface;
forming a first gate stack and a second gate stack on opposing sides of, and contacting, the first portion of the dummy fin, wherein the first gate stack and the second gate stack comprise a first gate dielectric and a second gate dielectric, respectively, and wherein sidewalls of the first gate dielectric and the second gate dielectric are in physical contact with the gate isolation region;
forming a contact etch stop layer on opposing sidewalls and a second top surface of the second portion of the dummy fin; and
forming an inter-layer dielectric over the contact etch stop layer.
10. The method of claim 9 , wherein the first gate stack and the second gate stack are formed on a first semiconductor fin and a second semiconductor fin, respectively.
11. The method of claim 9 , wherein a first high-k dielectric layer of the first gate stack and a second dielectric layer of the second gate stack are in direct contact with both of the gate isolation region and the first portion of the dummy fin.
12. The method of claim 9 , wherein the dummy fin and the gate isolation region are formed of different materials.
13. The method of claim 9 , wherein the gate isolation region extends laterally beyond edges of the dummy fin, and the gate isolation region comprises bottom corners with right angles.
14. The method of claim 9 , wherein the gate isolation region extends laterally beyond respective edges of the dummy fin.
15. The method of claim 9 , wherein after the dummy gate dielectric is removed from the first portion of the dummy fin, a second portion of the dummy gate dielectric is left on the second portion of the dummy fin.
16. The method of claim 15 , wherein the second portion of the dummy gate dielectric is between the contact etch stop layer and the second portion of the dummy fin.
17. A method comprising:
forming isolation regions extending into a semiconductor substrate;
forming a first protruding semiconductor fin and a second protruding semiconductor fin parallel to each other and protruding higher than the isolation regions;
forming a dummy fin between the first protruding semiconductor fin and the second protruding semiconductor fin, wherein the dummy fin is formed of a homogeneous dielectric material, and wherein a bottom surface of the dummy fin contacts a top surface of one of the isolation regions to form a horizontal interface;
forming a dummy gate dielectric on the dummy fin;
forming a first gate stack and a second gate stack extending on top surfaces and sidewalls of the first protruding semiconductor fin and the second protruding semiconductor fin, respectively, wherein the first gate stack and the second gate stack comprise a first gate dielectric and a second gate dielectric, respectively;
removing a first portion of the dummy gate dielectric from a first portion of the dummy fin, wherein the first portion of the dummy fin is between the first gate stack and the second gate stack, wherein after the first portion of the dummy gate dielectric is removed, a second portion of the dummy gate dielectric is left on a second portion of the dummy fin, and wherein the second portion of the dummy fin is between a first source/drain region and a second source/drain region; and
forming a gate isolation region between the first gate stack and the second gate stack, wherein the gate isolation region is over and contacting the dummy fin, and wherein sidewalls of the first gate dielectric and the second gate dielectric are in physical contact with the gate isolation region to form vertical interfaces.
18. The method of claim 17 further comprising:
forming a contact etch stop layer on, and physically contacting, opposing sidewalls of the dummy fin.
19. The method of claim 17 , wherein the gate isolation region and the dummy fin form a horizontal interface.
20. The method of claim 17 , wherein the gate isolation region extends laterally beyond opposing edges of the dummy fin.