Asynchronous interrupt event handling in multi-plane memory devices
A memory device includes a memory array configured with a plurality of memory planes, and control logic, operatively coupled with the memory array. The control logic performs a plurality of asynchronous memory access operations on the plurality of memory planes, detects an occurrence of an asynchronous interrupt event, and initiates a termination procedure for each of the plurality of asynchronous memory access operations to permit each of the plurality of asynchronous memory access operations to end at different times. In response to a first memory access operation of the plurality of asynchronous memory access operations ending, the control logic asserts a command result signal, wherein the command result signal is de-asserted automatically in response to receipt of a subsequent memory access command directed to any of the plurality of memory planes, and asserts a persistent event register signal, wherein the command result signal is de-asserted in response to receipt of a clear event register command.
1. A memory device comprising:
a memory array configured with a plurality of memory planes; and
control logic, operatively coupled with the memory array, to perform operations comprising:
performing a plurality of asynchronous memory access operations on the plurality of memory planes;
detecting an occurrence of an asynchronous interrupt event;
initiating a termination procedure for each of the plurality of asynchronous memory access operations to permit each of the plurality of asynchronous memory access operations to end at different times; and
in response to a first memory access operation of the plurality of asynchronous memory access operations ending:
asserting a command result signal, wherein the command result signal is de-asserted automatically in response to receipt of a subsequent memory access command directed to any of the plurality of memory planes; and
asserting a persistent event register signal, wherein the command result signal is de-asserted in response to receipt of a clear event register command.
2. The memory device of claim 1 , wherein the command result signal and the persistent event register signal are provided to at least one of a memory sub-system controller or a host system coupled to the memory device.
3. The memory device of claim 2 , wherein the persistent event register signal is to notify the at least one of the memory sub-system controller or the host system that the memory device has recovered from the occurrence of the asynchronous interrupt event and that the plurality of asynchronous memory access operations were terminated.
4. The memory device of claim 2 , wherein the control logic is to perform operations further comprising:
receiving the clear event register command from the at least one of the memory sub-system controller or the host system; and
de-asserting the persistent event register signal.
5. The memory device of claim 2 , wherein detecting the occurrence of the asynchronous interrupt event comprises at least one of receiving a reset command from the at least one of the memory sub-system controller or the host system, or detecting a drop in a voltage supply level of the memory device.
6. The memory device of claim 1 , wherein the command result signal and the persistent event register signal are asserted based on a value stored in a device status register representing a state of the plurality of asynchronous memory access operations on each of the plurality of memory planes.
7. The memory device of claim 1 , wherein performing the plurality of asynchronous memory access operations comprises performing a respective one of the plurality of asynchronous memory access operations on each of the plurality of memory planes concurrently.
8. The memory device of claim 1 , wherein initiating the termination procedure for each of the plurality of asynchronous memory access operations comprises causing a respective state machine associated with a respective one of the plurality of memory planes to enter one or more states to terminate a corresponding one of the plurality of asynchronous memory access operations being performed on the respective one of the plurality of memory planes.
9. The memory device of claim 1 , wherein the control logic is to perform operations further comprising:
in response to each of the plurality of asynchronous memory access operations ending, asserting a respective partition status signal indicating that a corresponding one of the plurality of memory planes is ready and able to accept a subsequent memory access command.
10. The memory device of claim 1 , wherein the control logic is to perform operations further comprising:
in response to all of the plurality of asynchronous memory access operations ending, asserting a device status signal indicating that all of the plurality of memory planes are ready and able to accept subsequent memory access commands.
11. A method comprising:
performing a plurality of asynchronous memory access operations on a plurality of memory planes of a memory device;
detecting an occurrence of an asynchronous interrupt event;
initiating a termination procedure for each of the plurality of asynchronous memory access operations to permit each of the plurality of asynchronous memory access operations to end at different times; and
in response to a first memory access operation of the plurality of asynchronous memory access operations ending:
asserting a command result signal, wherein the command result signal is de-asserted automatically in response to receipt of a subsequent memory access command directed to any of the plurality of memory planes; and
asserting a persistent event register signal, wherein the command result signal is de-asserted in response to receipt of a clear event register command.
12. The method of claim 11 , wherein the command result signal and the persistent event register signal are provided to at least one of a memory sub-system controller or a host system coupled to the memory device.
13. The method of claim 12 , wherein the persistent event register signal is to notify the at least one of the memory sub-system controller or the host system that the memory device has recovered from the occurrence of the asynchronous interrupt event and that the plurality of asynchronous memory access operations were terminated.
14. The method of claim 12 , further comprising:
receiving the clear event register command from the at least one of the memory sub-system controller or the host system; and
de-asserting the persistent event register signal.
15. The method of claim 12 , wherein detecting the occurrence of the asynchronous interrupt event comprises at least one of receiving a reset command from the at least one of the memory sub-system controller or the host system, or detecting a drop in a voltage supply level of the memory device.
16. The method of claim 11 , wherein the command result signal and the persistent event register signal are asserted based on a value stored in a device status register representing a state of the plurality of asynchronous memory access operations on each of the plurality of memory planes.
17. The method of claim 11 , wherein performing the plurality of asynchronous memory access operations comprises performing a respective one of the plurality of asynchronous memory access operations on each of the plurality of memory planes concurrently.
18. The method of claim 11 , wherein initiating the termination procedure for each of the plurality of asynchronous memory access operations comprises causing a respective state machine associated with a respective one of the plurality of memory planes to enter one or more states to terminate a corresponding one of the plurality of asynchronous memory access operations being performed on the respective one of the plurality of memory planes.
19. The method of claim 11 , further comprising:
in response to each of the plurality of asynchronous memory access operations ending, asserting a respective partition status signal indicating that a corresponding one of the plurality of memory planes is ready and able to accept a subsequent memory access command.
20. The method of claim 11 , further comprising:
in response to all of the plurality of asynchronous memory access operations ending, asserting a device status signal indicating that all of the plurality of memory planes are ready and able to accept subsequent memory access commands.