Artificial intelligence processor and method of processing deep-learning operation using the same

1. An Artificial Intelligence (AI) processor, comprising:

multiple Non-Volatile Memory (NVM) AI cores for respectively performing fixed-bit Multiply and Accumulation (MAC) operations required for a deep-learning operation based on data stored in NVM;

Static Random-Access Memory (SRAM) for storing at least part of results of the fixed-bit MAC operations; and

an AI core for performing an accumulation operation on the results of the fixed-bit MAC operations,

wherein the AI core generates an expanded bit operation result by accumulating the results of the fixed-bit MAC operations which are stored in the SRAM.

2. The AI processor of claim 1 , wherein:

the fixed-bit MAC operation is a 4-bit Multiply and Accumulation (MAC) operation, and

the expanded bit operation result corresponds to 8 bits.

3. The AI processor of claim 1 , wherein:

part of the NVM AI cores and the AI core are power-gated depending on a bit width required for the deep-learning operation.

4. The AI processor of claim 3 , wherein:

the bit width required for the deep-learning operation is set for each layer corresponding to the deep-learning operation.

5. The AI processor of claim 1 , further comprising:

an AI DRAM controller for providing weights required for the fixed-bit MAC operations to the NVM based on AI data stored in DRAM.

6. The AI processor of claim 5 , wherein:

the AI DRAM controller reads features required for the fixed-bit MAC operations from the DRAM and stores the features in the SRAM.

7. The AI processor of claim 6 , wherein:

the AI DRAM controller stores only nonzero weights in the NVM.

8. The AI processor of claim 7 , wherein:

the AI DRAM controller reads only features to be multiplied by nonzero weights from the DRAM.

9. The AI processor of claim 8 , wherein:

the AI DRAM controller includes

a Direct Memory Access (DMA) unit for performing control for reading data from the DRAM and writing data to the DRAM;

a sparse weight unit for providing nonzero weight information to the DMA unit; and

a DRAM protocol converter for writing data to the DRAM or reading data from the DRAM based on control of the DMA unit.

10. The AI processor of claim 1 , wherein:

each of the NVM AI cores includes

an NVM array; and

a MAC operator for performing a MAC operation based on data read from the NVM array.

11. A method for processing a deep-learning operation, comprising:

performing, by respective multiple Non-Volatile Memory (NVM) AI cores, fixed-bit Multiply and Accumulation (MAC) operations required for a deep-learning operation based on data stored in NVM;

storing at least part of results of the fixed-bit MAC operations in SRAM;

performing, by an AI core, an accumulation operation on the results of the fixed-bit MAC operations; and

storing a result of the accumulation operation in the SRAM,

wherein the AI core generates an expanded bit operation result by accumulating the results of the fixed-bit MAC operations which are stored in SRAM.

12. The method of claim 11 , wherein:

the fixed-bit MAC operation is a 4-bit Multiply and Accumulation (MAC) operation, and the expanded bit operation result corresponds to 8 bits.

13. The method of claim 11 , wherein:

part of the NVM AI cores and the AI core are power-gated depending on a bit width required for the deep-learning operation.

14. The method of claim 13 , wherein:

the bit width required for the deep-learning operation is set for each layer corresponding to the deep-learning operation.

15. The method of claim 11 , wherein:

the SRAM stores features required for the fixed-bit MAC operations.

16. The method of claim 15 , wherein:

the NVM stores only nonzero weights.