IP Library Granted Patent US 11,842,895
Granted Patent B2
US 11,842,895 · App. 17/427,676 · Granted Dec 12, 2023

Semiconductor device and power conversion device

Inventors: Kohei Ebihara (Tokyo, JP); Takaaki Tominaga (Tokyo, JP)
Assignee: MITSUBISHI ELECTRIC CORPORATION
H01L29/417H01L29/0619H01L29/41741H01L29/7811H02M1/08H01L23/293H01L23/3171H01L29/1608H02M7/53871H02P27/08
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Quick Facts
Patent No.
US 11,842,895
App. No.
17/427,676
Granted
Dec 12, 2023
Kind
B2
Abstract

An SBD includes: a terminal well region formed to surround an active region; a field insulating film formed to cover part of the terminal well region; a surface electrode formed on a drift layer on an inner side in relation to the field insulating film and electrically connected to the terminal well region; a surface protection film covering an end portion on an outer side of the surface electrode; and a back surface electrode formed on a back surface of a single crystal substrate. An end portion of an outer side of the surface electrode in the corner portion of the terminal region is located on an inner side in relation to the end portion of the outer side of the surface electrode in a straight portion of a terminal region based on a position of an end portion of an outer side of the terminal well region.

Claims (55)

1. A semiconductor device, comprising:

a semiconductor substrate made up of silicon carbide;

a drift layer of a first conductivity type formed on the semiconductor substrate and made up of silicon carbide;

a well region of a second conductivity type formed on a surface layer portion of the drift layer in an active region;

a source region of the first conductivity type formed on a surface layer portion of the well region;

a gate insulating film covering a channel region which is a region located between the source region and the drift layer in the well region;

a gate electrode formed on the gate insulating film;

an interlayer insulating film covering the gate electrode;

at least one terminal well region of the second conductivity type formed on the surface layer portion of the drift layer to surround the active region in a plan view in a terminal region outside the active region;

a field insulating film formed to cover part of the terminal well region on the drift layer;

a surface electrode formed on the drift layer on an inner side in relation to the field insulating film, electrically connected to the terminal well region and having a portion made up of metal including one or a plurality of Al, Cu, Mo, and Ni or Al alloy as a material;

an upper surface film formed on the field insulating film and the surface electrode to cover an end portion on an outer side of the surface electrode; and

a back surface electrode formed on a back surface of the semiconductor sub strate, wherein

the surface electrode includes:

a source electrode formed on the interlayer insulating film and electrically connected to the source region through a contact hole formed in the interlayer insulating film; and

a gate wiring formed on the interlayer insulating film to surround the source electrode in a plan view and electrically connected to the gate electrode through a contact hole formed in the interlayer insulating film,

the terminal region includes a straight portion and a curved corner portion in a plan view,

the end portion of the outer side of the surface electrode is located on an inner side in relation to the end portion of the outer side of the terminal well region, and

with respect to a distance from the end portion on the outer side of the terminal well region to the end portion on the outer side of the surface electrode, the distance in the corner portion of the terminal region is larger than the distance in the straight portion of the terminal region.

2. The semiconductor device according to claim 1 , wherein

the terminal well region includes a boundary region and an extension region extending outside from the boundary region and having a lower impurity concentration than the boundary region.

3. The semiconductor device according to claim 2 , wherein

the impurity concentration of the extension region is lower than an impurity concentration of the well region.

4. The semiconductor device according to claim 2 , wherein

a dose amount of the extension region is equal to or larger than 0.5×10 13 /cm 2 and equal to or smaller than 5×10 13 /cm 2 .

5. The semiconductor device according to claim 2 , wherein

the impurity concentration of the extension region is equal to or larger than 1×10 17 /cm 3 and equal to or smaller than 5×10 19 /cm 3 .

6. A power conversion device, comprising:

a main conversion circuit including the semiconductor device according to claim 1 , converting electrical power which has been input, and outputting the electrical power;

a drive circuit outputting a drive signal for driving the semiconductor device to the semiconductor device; and

a control circuit outputting a control signal for controlling the drive circuit to the drive circuit.

7. A semiconductor device, comprising:

a semiconductor substrate;

a drift layer of a first conductivity type formed on the semiconductor substrate;

at least one terminal well region of a second conductivity type formed on a surface layer portion of the drift layer to surround an active region in a plan view in a terminal region outside the active region;

a field insulating film formed to cover part of the terminal well region on the drift layer;

a surface electrode formed on the drift layer on an inner side in relation to the field insulating film and electrically connected to the terminal well region;

an upper surface film formed on the field insulating film and the surface electrode to cover an end portion on an outer side of the surface electrode; and

a back surface electrode formed on a back surface of the semiconductor substrate, wherein

the terminal region includes a straight portion and a corner portion in a plan view,

an end portion of an outer side of the surface electrode in the corner portion of the terminal region is located on an inner side in relation to the end portion of the outer side of the surface electrode in the straight portion of the terminal region based on a position of an end portion of an outer side of the terminal well region,

the end portion of the outer side of the surface electrode is located on an outer side in relation to the end portion of the outer side of the terminal well region, and

with respect to a distance from the end portion on the outer side of the terminal well region to the end portion on the outer side of the surface electrode, the distance in the corner portion of the terminal region is smaller than the distance in the straight portion of the terminal region.

8. The semiconductor device according to claim 1 , comprising

the plurality of terminal well regions formed separately from each other in a nested form.

9. The semiconductor device according to claim 7 , comprising

he plurality of terminal well regions formed separately from each other in a nested form.

10. The semiconductor device according to claim 8 , wherein

the surface electrode is electrically connected to at least one of the plurality of terminal well regions.

11. The semiconductor device according to claim 9 , wherein

the surface electrode is electrically connected to at least one of the plurality of terminal well regions.

12. A power conversion device, comprising:

a main conversion circuit including the semiconductor device according to claim 7 , converting electrical power which has been input, and outputting the electrical power;

a drive circuit outputting a drive signal for driving the semiconductor device to the semiconductor device; and

a control circuit outputting a control signal for controlling the drive circuit to the drive circuit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 2, 2021
From: EBIHARA, KOHEI; TOMINAGA, TAKAAKI
To: MITSUBISHI ELECTRIC CORPORATION
Reel/Frame 057049/0766 →
Continuity (1)
Related Publication 20220149163A1 · May 12, 2022