In-situ formation of metal gate modulators
A method includes forming a gate dielectric on a semiconductor region, depositing a work-function layer over the gate dielectric, depositing a silicon layer over the work-function layer, and depositing a glue layer over the silicon layer. The work-function layer, the silicon layer, and the glue layer are in-situ deposited. The method further includes depositing a filling-metal over the glue layer; and performing a planarization process, wherein remaining portions of the glue layer, the silicon layer, and the work-function layer form portions of a gate electrode.
1. A method comprising:
forming a first gate dielectric on a first semiconductor region;
depositing a first work-function layer over the first gate dielectric;
performing a soaking process to deposit a first silicon layer over the first work-function layer, wherein the soaking process is performed using a silicon-containing process gas;
depositing a first glue layer over the first silicon layer, wherein the first work-function layer, the first silicon layer, and the first glue layer are deposited using oxygen-free process gases;
depositing a first filling-metal over the first glue layer; and
performing a planarization process, wherein remaining portions of the first glue layer, the first silicon layer, and the first work-function layer form portions of a gate electrode.
2. The method of claim 1 , wherein at a time the first silicon layer is deposited, the first silicon layer comprises elemental silicon.
3. The method of claim 1 , wherein the first silicon layer is deposited by thermally soaking a wafer that comprises the first work-function layer in a silicon-based precursor.
4. The method of claim 3 , wherein the thermally soaking is performed at a temperature in a range between about 300° C. and about 500° C.
5. The method of claim 1 further comprising:
forming a second gate dielectric on a second semiconductor region;
depositing a metal-containing layer over the second gate dielectric;
depositing a second work-function layer over the metal-containing layer, wherein the metal-containing layer and the second work-function layer are formed of different materials;
depositing a second silicon layer over the second work-function layer;
depositing a second glue layer over the second silicon layer, wherein the second work-function layer, the second silicon layer, and the second glue layer are in-situ performed; and
depositing a second filling-metal over the second glue layer.
6. The method of claim 1 , wherein during an entire period of time starting at a first time the depositing the first work-function layer is started and ending at a second time the depositing the first glue layer is finished, a corresponding wafer comprising the first semiconductor region is in a vacuum environment.
7. The method of claim 1 , wherein the silicon-containing process gas comprises silane.
8. A method comprising:
forming a gate dielectric over a semiconductor region;
depositing a work-function layer over the gate dielectric;
depositing a silicon layer over the work-function layer, wherein the silicon layer is an electrically conductive layer;
depositing a glue layer over and contacting the silicon layer, wherein an interface between the silicon layer and the glue layer is free from oxygen; and
forming a filling-metal region over and contacting the glue layer.
9. The method of claim 8 , wherein the depositing the glue layer comprises depositing a silicon nitride layer.
10. The method of claim 8 , wherein the silicon layer comprises elemental silicon atoms.
11. The method of claim 8 , wherein the depositing the silicon layer comprising thermal soaking the work-function layer in a silicon-containing precursor.
12. The method of claim 8 , wherein the semiconductor region comprises a semiconductor fin, and wherein the gate dielectric is formed on both of a top surface and sidewalls of the semiconductor fin.
13. The method of claim 8 , wherein the work-function layer, the silicon layer, and the glue layer are in-situ deposited without vacuum break in between.
14. The method of claim 8 , wherein the work-function layer is an n-work-function layer.
15. The method of claim 8 , wherein the silicon layer has a thickness smaller than about 10 Å.
16. A method comprising:
forming a high-k dielectric layer on a semiconductor fin;
forming a work-function layer over the high-k dielectric layer;
depositing a first titanium nitride layer over the work-function layer;
depositing a silicon layer over the first titanium nitride layer;
depositing a second titanium nitride layer over the silicon layer, wherein an interface between the silicon layer and the second titanium nitride layer is free from oxygen; and
forming a filling-metal region over and contacting the second titanium nitride layer.
17. The method of claim 16 , wherein the silicon layer is configured to electrically interconnect the first titanium nitride layer and the second titanium nitride layer.
18. The method of claim 16 , wherein the silicon layer comprises elemental silicon.
19. The method of claim 16 , wherein the silicon layer is free from silicon oxide therein.
20. The method of claim 16 , wherein the work-function layer, the first titanium nitride layer, the silicon layer, and the second titanium nitride layer are deposited in a same vacuum environment.