IP Library Granted Patent US 11,843,049
Granted Patent B2
US 11,843,049 · App. 17/533,056 · Granted Dec 12, 2023

Lateral diffused metal oxide semiconductor device

Inventor: Zong-Han Lin (Tainan, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L29/7816H01L29/0649H01L29/41791H01L29/7851
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Quick Facts
Patent No.
US 11,843,049
App. No.
17/533,056
Granted
Dec 12, 2023
Kind
B2
Abstract

A lateral diffused metal oxide semiconductor (LDMOS) device includes a first fin-shaped structure on a substrate, a second fin-shaped structure adjacent to the first fin-shaped structure, a shallow trench isolation (STI) between the first fin-shaped structure and the second fin-shaped structure, a first gate structure on the first fin-shaped structure, a second gate structure on the second fin-shaped structure, and an air gap between the first gate structure and the second gate structure.

Claims (40)

1. A lateral diffused metal oxide semiconductor (LDMOS) device, comprising:

a first fin-shaped structure on a substrate;

a second fin-shaped structure adjacent to the first fin-shaped structure;

a third fin-shaped structure between the first fin-shaped structure and the second fin-shaped structure;

a first shallow trench isolation (STI) between the first fin-shaped structure and the third fin-shaped structure;

a second STI between the second fin-shaped structure and the third fin-shaped structure;

a first gate structure on the first fin-shaped structure;

a second gate structure on the second fin-shaped structure;

a third gate structure on the third fin-shaped structure; and

a first air gap between the first gate structure and the third gate structure.

2. The LDMOS device of claim 1 , further comprising:

a source region adjacent to one side of the first gate structure on the first fin-shaped structure;

a drain region adjacent to one side of the second gate structure on the second fin-shaped structure;

an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; and

a first contact plug on the source region; and

a second contact plug on the drain region.

3. The LDMOS device of claim 2 , wherein the first air gap is in the ILD layer.

4. The LDMOS device of claim 1 , wherein a width of the second gate structure is less than a width of the first gate structure.

5. The LDMOS device of claim 1 , wherein the first air gap is directly on the STI.

6. The LDMOS device of claim 1 , wherein the first gate structure and the second gate structure comprise metal gates.

7. The LDMOS device of claim 1 , further comprising a second air gap between the second gate structure and the third gate structure.

8. The LDMOS device of claim 7 , wherein the second air gap is directly on the STI.

9. A lateral diffused metal oxide semiconductor (LDMOS) device, comprising:

a first fin-shaped structure on a substrate;

a second fin-shaped structure adjacent to the first fin-shaped structure;

a shallow trench isolation (STI) between the first fin-shaped structure and the second fin-shaped structure;

a first gate structure on the first fin-shaped structure;

a second gate structure on the second fin-shaped structure;

a third gate structure on the STI; and

a first air gap between the first gate structure and the third gate structure.

10. The LDMOS device of claim 9 , further comprising:

a source region adjacent to one side of the first gate structure on the first fin-shaped structure;

a drain region adjacent to one side of the second gate structure on the second fin-shaped structure;

an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; and

a first contact plug on the source region; and

a second contact plug on the drain region.

11. The LDMOS device of claim 10 , wherein the first air gap is in the ILD layer.

12. The LDMOS device of claim 9 , wherein a width of the second gate structure is less than a width of the first gate structure.

13. The LDMOS device of claim 9 , wherein the first gate structure and the second gate structure comprise metal gates.

14. The LDMOS device of claim 13 , further comprising a second air gap between the second gate structure and the third gate structure.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 22, 2021
From: LIN, ZONG-HAN
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 058187/0662 →
Priority Claims (1)
CN 202111263331.0 · Oct 26, 2021 · national
Continuity (1)
Related Publication 20230130955A1 · Apr 27, 2023