IP Library › Granted Patent US 11,843,883
Granted Patent B2
US 11,843,883 · App. 17/619,348 · Granted Dec 12, 2023

Solid-state imaging device and electronic device

Inventors: Masayuki Tachi (Kanagawa, JP); Kazuhito Kobayashi (Kanagawa, JP); Daisuke Yoshioka (Kanagawa, JP); Shiro Omori (Kanagawa, JP); Takeshi Kozasa (Fukuoka, JP); Kazuhide Fujita (Kanagawa, JP); Naoto Hayashida (Kanagawa, JP); Shoyu Tanaka (Kanagawa, JP)
Assignee: Sony Semiconductor Solutions Corporation
H04N25/704H04N25/44H04N25/46H04N25/533H04N25/583H04N25/77
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Quick Facts
Patent No.
US 11,843,883
App. No.
17/619,348
Granted
Dec 12, 2023
Kind
B2
Abstract

The present disclosure relates to a solid-state imaging device that makes it possible to suppress deterioration of phase difference information, and an electronic device. There is provided a solid-state imaging device including a pixel array unit in which a plurality of pixels is two-dimensionally arrayed. The plurality of pixels includes a phase difference pixel for phase difference detection, the pixel array unit has an array pattern in which pixel units including neighboring pixels of a same color are regularly arrayed, and the phase difference pixel is partially not added when horizontal/vertical addition is performed on a pixel signal of a predetermined pixel in a horizontal direction and a pixel signal of a predetermined pixel in a vertical direction, in reading the plurality of pixels. The present disclosure can be applied to, for example, a CMOS image sensor having a phase difference pixel.

Claims (64)

1. A solid-state imaging device, comprising:

a pixel array unit in which a plurality of pixels is two-dimensionally arrayed,

wherein the plurality of pixels includes sets of phase difference pixels for phase difference detection, each of the sets including a respective first phase difference pixel and a respective second phase difference pixel adjacent to each other;

wherein the pixel array unit has an array pattern in which a plurality of pixel units, each of the pixel units including neighboring pixels of a same respective color, are regularly arrayed; and

wherein, in reading the plurality of pixels,

pixel signals of a first subset of the phase difference pixels are added in a first pattern of horizontal and vertical addition, and

pixel signals of a second subset of the phase difference pixels are discarded in a second pattern of the horizontal and vertical addition.

2. The solid-state imaging device according to claim 1 , wherein

a density of the phase difference pixels after the horizontal and vertical addition is a density that is same as or lower than a density of the phase difference pixels before the horizontal and vertical addition.

3. The solid-state imaging device according to claim 1 , wherein

there is provided, in a horizontal direction, a plurality of selection control lines to select connection to a vertical signal line from a floating diffusion region formed for every group of the pixel units in a vertical direction, and

driving of the plurality of selection control lines is controlled at a time of the horizontal and vertical addition.

4. The solid-state imaging device according to claim 1 , wherein

an exposure time of a pixel included in an individual pixel unit is adjusted for every pixel, and

in reading the plurality of pixels, a high dynamic range (HDR) signal is generated by synthesizing pixel signals that are obtained by the horizontal and vertical addition and have a same color but different exposure times.

5. The solid-state imaging device according to claim 4 , wherein

among the plurality of pixels, the respective first phase difference pixel and the respective second phase difference pixel are adjacent pixels of a same color included in adjacent different pixel units.

6. The solid-state imaging device according to claim 5 , wherein

the individual pixel unit includes four pixels in a 2×2 arrangement, and

the respective first phase difference pixel and the respective second phase difference pixel are adjusted to have a same exposure time.

7. The solid-state imaging device according to claim 4 , wherein

each of the phase difference pixels is configured as a light-shielded pixel.

8. The solid-state imaging device according to claim 1 , wherein

in pixels included in an individual pixel unit, all pixels of the same respective color have a same exposure time, and

in reading the plurality of pixels, the horizontal and vertical addition is performed after addition of pixel signals of pixels of the same respective color included in the individual pixel unit.

9. The solid-state imaging device according to claim 8 , wherein

among the plurality of pixels, the respective first phase difference pixel and the respective second phase difference pixel are adjacent pixels of a same color included in adjacent different pixel units.

10. The solid-state imaging device according to claim 9 , wherein

the pixel unit includes four pixels in a 2×2 arrangement, and

the respective first phase difference pixel and the respective second phase difference pixel are adjusted to have a same exposure time.

11. The solid-state imaging device according to claim 8 , wherein

each of the phase difference pixels is configured as a light-shielded pixel.

12. The solid-state imaging device according to claim 3 , wherein

in the horizontal and vertical addition, pixel signals of predetermined two pixels in a horizontal direction and pixel signals of two corresponding pixels in a vertical direction are added, and

in the first pattern of the horizontal and vertical addition, driving of a plurality of selection control lines is controlled in such a way that a pixel signal of a phase difference pixel included in a specific pixel unit is selected, and a pixel signal of a normal pixel included in pixel units other than the specific pixel unit is not added.

13. The solid-state imaging device according to claim 12 , wherein

in the second pattern of the horizontal and vertical addition, driving of a plurality of selection control lines is controlled in such a way that addition is not performed on a pixel signal of a pixel included in a pixel unit that includes a specific phase difference pixel and a pixel signal of a normal pixel included in a pixel unit diagonal to the pixel unit that includes the specific phase difference pixel.

14. The solid-state imaging device according to claim 13 , wherein

in a third pattern of the horizontal and vertical addition, driving of a plurality of selection control lines is controlled in such a way that a pixel signal of a pixel of a pixel unit including only normal pixels is added.

15. The solid-state imaging device according to claim 3 , wherein

a specific floating diffusion region is connected to a common vertical signal line, and

in the horizontal and vertical addition, driving of a plurality of selection control lines is controlled in order to read a pixel signal from the specific floating diffusion region.

16. The solid-state imaging device according to claim 15 , wherein

the specific floating diffusion region connected to the common vertical signal line is formed in different columns in the vertical direction, and

each of pixel units sharing the specific floating diffusion region is arranged in a same row in the horizontal direction and includes pixels of a same color.

17. A solid-state imaging device comprising:

a pixel array unit in which a plurality of pixels is two-dimensionally arrayed,

wherein the plurality of pixels includes sets of phase difference pixels for phase difference detection, each of the sets including a respective first phase difference pixel and a respective second phase difference pixel adjacent to each other;

wherein the pixel array unit has an array pattern in which a plurality of pixel units, each of the pixel units including neighboring pixels of a same respective color, are regularly arrayed;

wherein there is provided, in a horizontal direction, a plurality of selection control lines to select connection to a vertical signal line from a floating diffusion region formed for every group of the pixel units in a vertical direction; and

wherein driving of the plurality of selection control lines is controlled to enable at least a first pattern and a different second pattern of horizontal and vertical addition in reading the plurality of pixels.

18. The solid-state imaging device according to claim 17 , wherein

an exposure time of a pixel included in an individual pixel unit is adjusted for every pixel, and

in reading the plurality of pixels, a high dynamic range (HDR) signal is generated by synthesizing pixel signals that have a same color but different exposure times and are obtained by the horizontal and vertical addition.

19. The solid-state imaging device according to claim 17 , wherein in said reading the plurality of pixels,

pixel signals of a first subset of the phase difference pixels are added in the first pattern of the horizontal and vertical addition, and

pixel signals of a second subset of the phase difference pixels are discarded in the different second pattern of the horizontal and vertical addition.

20. An electronic device equipped with a solid-state imaging device, the solid-state imaging device comprising:

a pixel array unit in which a plurality of pixels is two-dimensionally arrayed,

wherein the plurality of pixels includes sets of phase difference pixels for phase difference detection, each of the sets including a respective first phase difference pixel and a respective second phase difference pixel adjacent to each other;

wherein the pixel array unit has an array pattern in which a plurality of pixel units, each of the pixel units including neighboring pixels of a same respective color, are regularly arrayed; and

wherein, in reading the plurality of pixels,

pixel signals of a first subset of the phase difference pixels are added in a first pattern of horizontal and vertical addition, and

pixel signals of a second subset of the phase difference pixels are discarded in a second pattern of the horizontal and vertical addition.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 28, 2021
From: TACHI, MASAYUKI; KOBAYASHI, KAZUHITO; YOSHIOKA, DAISUKE; OMORI, SHIRO; KOZASA, TAKESI; FUJITA, KAZUHIDE; HAYASHIDA, NAOTO; TANAKA, SHOYU
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 058490/0637 →
Priority Claims (1)
JP 2019-117530 · Jun 25, 2019 · national
Continuity (1)
Related Publication 20220345651A1 · Oct 27, 2022