Process for preparing a channel region of a thin-film transistor in a 3-dimensional thin-film transistor array
A process includes (a) providing a semiconductor substrate having a planar surface; (b) forming a plurality of thin-film layers above the planar surface of the semiconductor substrate, one on top of another, including among the thin-film layers first and second isolation layers, wherein a significantly greater concentration of a first dopant specie is provided in the first isolation layer than in the second isolation layer; (c) etching along a direction substantially orthogonal to the planar surface through the thin-films to create a trench having sidewalls that expose the thin-film layers; (d) depositing conformally a semiconductor material on the sidewalls of the trench; (e) annealing the first isolation layer at a predetermined temperature and a predetermined duration such that the first isolation layer act as a source of the first dopant specie which dopes a portion of the semiconductor material adjacent the first isolation layer; and (f) selectively etching the semiconductor material to remove the doped portion of the semiconductor material without removing the remainder of the semiconductor material.
1. A process, comprising:
forming a plurality of thin-film layers successively above a planar surface of a substrate, wherein the thin-film layers include first and second isolation layers, and a plurality of active layers, each active layer comprising a material suitable for forming a drain region or a source region of a thin-film transistor, wherein the first isolation layer is formed between and in contact with two active layers and wherein the first isolation layer has a greater concentration of a first dopant specie than the second isolation layer;
forming a trench through the thin-films to expose the thin-films on sidewalls of the trench;
depositing conformally a semiconductor material on the sidewalls of the trench;
bringing the first isolation layer to a predetermined temperature for a predetermined duration, such that a portion of the first dopant specie diffuses out of the first isolation layer to dope a portion of the semiconductor material; and
selectively etching the semiconductor material, such that the doped portion of the semiconductor material is removed.
2. The process of claim 1 , further comprising etching the thin-film layers such that the first isolation layer recesses from the sidewalls of the trench.
3. The process of claim 1 wherein the semiconductor material comprises at least one of: an amorphous silicon and a polysilicon.
4. The process of claim 1 , wherein the selective etching comprises a dry etching step.
5. The process of claim 1 , wherein the first dopant specie comprises boron.
6. The process of claim 5 , wherein (i) the first isolation layer comprises one or more of: an organosilicon layer, a silicon nitride layer and a silicate glass, and (ii) the selective etching uses an etchant that comprises at least one of: tetra-methyl ammonium hydroxide (TMAH), potassium hydroxide (KOH), and ethylene diamine and pyrocatechol (EDP).
7. The process of claim 6 , wherein the organosilicate layer comprises SiOCH or SiOC.
8. The process of claim 6 , wherein the first isolation layer comprises a carbon-doped layer having a carbon dopant concentration of about 10 20 cm −3 or greater, and wherein the selective etching uses an etchant that comprises ethylene diamine and pyrocatechol (EDP).
9. The process of claim 6 , wherein the predetermined temperature is achieved by a rapid thermal annealing step.
10. The process of claim 9 , wherein the predetermined temperature is between 650° C. and 820° C., preferably about 750° C.
11. The process of claim 1 , further comprising depositing a highly doped material adjacent and over the semiconductor material, the highly doped material comprises a second dopant specie.
12. The process of claim 11 , further comprising allowing the second dopant specie to diffuse into the semiconductor material to achieve an effective dopant concentration in the semiconductor material.
13. The process of claim 12 , wherein the effective dopant concentration determines a threshold voltage of a thin-film transistor in which the semiconductor material serve as a channel region.
14. The process of claim 11 , wherein the second dopant specie comprise phosphorus.
15. The process of claim 1 , wherein (i) the first isolation layer comprises one or more of: an organosilicon layer, a silicon nitride layer and a silicate glass, and (ii) the selective etching uses an etchant that comprises at least one of: atomic chlorine, HF and a fluorocarbon gas.
16. The process of claim 15 , wherein the predetermined temperature is achieved by a rapid thermal annealing step.
17. The process of claim 15 , wherein the predetermined temperature is between about 600° C. and about 820° C., preferably about 750° C.
18. The process of claim 15 , wherein the first dopant specie comprises phosphorus.
19. The process of claim 18 , wherein the etchant comprises an aqueous HF solution that includes both HF and one or more of: nitric acid and acetic acid.
20. The process of claim 15 , wherein the first isolation layer comprises a borosilicate glass or phosphorus silicate glass with a dopant concentration of boron or phosphorus greater than 1.0×10 22 cm −3 .
21. The process of claim 1 , further comprising depositing a capping layer over the conformally deposited semiconductor material.