Memory device and system

1. A memory device comprising:

an address generator which generates a first physical address and a second physical address different from the first physical address;

a first nonvolatile memory including the first physical address;

a second nonvolatile memory including the second physical address;

an attack detecting circuit which detects whether the first nonvolatile memory and the second nonvolatile memory are attacked, wherein the attack detecting circuit:

receives first data from the first nonvolatile memory,

receives second data from the second nonvolatile memory,

compares the first data and the second data with each other,

determines whether the first nonvolatile memory and the second nonvolatile memory are attacked based on a comparison result of the first data and the second data, and

generates an attack detecting signal in response to determining the first data and the second data are different from each other; and

a processor that performs a data protection operation comprising withholding a response to an external data read request in response to the generation of the attack detecting signal.

2. The memory device of claim 1 , wherein:

when the first data and the second data are different from each other, the attack detecting circuit determines that there is an attack on the first nonvolatile memory and the second nonvolatile memory, and

when the first data and the second data are identical to each other, the attack detecting circuit determines that there is no attack on the first nonvolatile memory and the second nonvolatile memory.

3. The memory device of claim 1 , wherein the data protection operation includes deletion of data stored at the first physical address and data stored at the second physical address.

4. The memory device of claim 1 , wherein:

the processor receives a first identifier and the external data read request for the first identifier, and

the processor converts the first identifier into a first logical address and provides the first logical address to the address generator.

5. The memory device of claim 4 , wherein:

the address generator operates the first logical address and a first physical address generation code to generate the first physical address, and

the address generator operates the first logical address and a second physical address generation code to generate the second physical address.

6. The memory device of claim 4 , wherein:

the address generator generates the first physical address, using the first logical address and a first lookup table, and

the address generator generates the second physical address, using the first logical address and a second lookup table.

7. The memory device of claim 1 , wherein:

the processor receives the external data read request,

the attack detecting circuit generates an attack non-detecting signal, when the first data and the second data are identical to each other, and

the processor outputs one of the first data and the second data when the attack non-detecting signal is generated.

8. The memory device of claim 7 , wherein:

the first nonvolatile memory is a single level cell (SLC) region of a flash memory,

the second nonvolatile memory is a multi-level cell (MLC) region of a flash memory, and

the processor outputs the first data, when the attack non-detecting signal is generated.

9. The memory device of claim 1 , further comprising:

a first error correction circuit connected to the first nonvolatile memory; and

a second error correction circuit connected to the second nonvolatile memory, wherein:

the first nonvolatile memory and the second nonvolatile memory include a first error correction code and a second error correction code, respectively,

the first error correction circuit generates the first data, using data stored in the first physical address and the first error correction code, and

the second error correction circuit generates the second data, using data stored in the second physical address and the second error correction code.

10. The memory device of claim 1 , wherein:

the processor receives a second identifier, third data associated with the second identifier, and a write request for the third data, wherein:

the address generator generates a third physical address, and a fourth physical address different from the third physical address, from the second identifier, and

in response to write request for the third data:

the processor stores the third data at the third physical address of the first nonvolatile memory, and

the processor stores the third data at the fourth physical address of the second nonvolatile memory.

11. A memory device comprising:

a first nonvolatile memory which stores first data at a first physical address corresponding to a first identifier;

a second nonvolatile memory in which second data different from the first data is stored at a second physical address corresponding to the first identifier and different from the first physical address;

an attack detecting circuit which detects whether the first nonvolatile memory and the second nonvolatile memory are attacked; and

a processor which receives a read request of data corresponding to the first identifier, wherein:

in response to the read request:

the processor accesses the first physical address of the first nonvolatile memory to read third data associated with the first data,

the processor accesses the second physical address of the second nonvolatile memory to read fourth data associated with the second data, and

the attack detecting circuit receives the third and fourth data and generates an attack detecting signal in response to determining the third data and the fourth data are different from each other; and

the processor that performs a data protection operation comprising withholding a response to the read request in response to the generation of the attack detecting signal.

12. The memory device of claim 11 , wherein in response to the read request:

the first nonvolatile memory provides the first data to the attack detecting circuit as the third data, and

the second nonvolatile memory provides the first data to the attack detecting circuit as the fourth data,

the attack detecting circuit generates an attack detecting signal, and

the processor performs a data protection operation of the first nonvolatile memory and the second nonvolatile memory, when the attack detecting signal is generated.