Systems, methods, and apparatus for tile configuration
Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address; and execution circuitry to execute the decoded instruction to set a tile configuration for the processor to utilize tiles in matrix operations based on a description retrieved from the memory address, wherein a tile a set of 2-dimensional registers are discussed.
1. A processor comprising:
decode circuitry to decode an instance of a single instruction having fields for an opcode and a memory address; and
execution circuitry to execute the decoded instance of the single instruction to set a tile configuration for the processor to utilize tiles in arithmetic or Boolean matrix operations based on a description retrieved from the memory address, wherein a tile is a set of 2-dimensional registers.
2. The processor of claim 1 , wherein the configuration comprises a palette identifier and details regarding a number of rows and columns per tile of the palette, wherein up to 8 tiles are to be detailed.
3. The processor of claim 2 , wherein the palette identifier is an index into a palette table defining a number of bytes per tile and bytes per row of the tile.
4. The processor of claim 1 , wherein the configuration is stored in a single packed data register.
5. The processor of claim 1 , wherein the configuration is stored in a plurality of packed data registers, one packed data register per configured tile.
6. The processor of claim 1 , wherein the execution circuitry to general a fault upon a value of a number of rows for a tile being zero and a number of columns for the row being non-zero.
7. The processor of claim 1 , wherein the description is 64 bytes in size.
8. A method comprising:
decoding an instance of a single instruction having fields for an opcode and a memory address; and
executing the decoded instance of the single instruction to set a tile configuration for a processor to utilize tiles in matrix operations based on a description retrieved from the memory address, wherein a tile is a set of 2-dimensional registers.
9. The method of claim 8 , wherein the configuration comprises a palette identifier and details regarding a number of rows and columns per tile of the palette.
10. The method of claim 9 , wherein the palette identifier is an index into a palette table defining a number of bytes per tile and bytes per row of the tile.
11. The method of claim 8 , wherein the configuration is stored in a single packed data register.
12. The method of claim 8 , wherein the configuration is stored in a plurality of packed data registers, one packed data register per configured tile.
13. The method of claim 8 , further comprising:
faulting upon a value of a number of rows for a tile being zero and a number of columns for the row being non-zero.
14. The method of claim 8 , wherein the description is 64 bytes in size.
15. A non-transitory machine-readable medium storing at least an instance of a single instruction which causes a processor to perform a method, the method comprising:
decoding the instance of the single instruction having fields for an opcode and a memory address; and
executing the decoded instance of the single instruction to set a tile configuration for the processor to utilize tiles in arithmetic or Boolean matrix operations based on a description retrieved from the memory address, wherein a tile is a set of 2-dimensional registers.
16. The non-transitory machine-readable medium of claim 15 , wherein the configuration comprises a palette identifier and details regarding a number of rows and columns per tile of the palette.
17. The non-transitory machine-readable medium of claim 16 , wherein the palette identifier is an index into a palette table defining a number of bytes per tile and bytes per row of the tile.
18. The non-transitory machine-readable medium of claim 15 , further comprising:
faulting upon a value of a number of rows for a tile being zero and a number of columns for the row being non-zero.
19. The processor of claim 1 , wherein bytes 2-15 of the description are zero.
20. The processor of claim 1 , wherein the description is further to indicate a row of a tile to be used to restart a matrix operation.