Semiconductor package and manufacturing method thereof

1. A method, comprising:

forming a conductive wiring over at least one device;

forming a polymer layer over the conductive wiring, wherein the polymer layer has a zeroth opening exposing a portion of the conductive wiring;

forming a seed layer over a top surface of the polymer layer, wherein the seed layer extends into the zeroth opening of the polymer layer;

forming a first patterned photoresist layer over the seed layer, wherein the first patterned photoresist layer comprises a first opening exposing a portion of the seed layer in the zeroth opening of the polymer layer;

forming a metallic wiring in the first opening and on the exposed portion of the seed layer, wherein the metallic wiring fills in the zeroth opening of the polymer layer;

forming a conductive via on the metallic wiring; and

removing the first patterned photoresist layer.

2. The method as claimed in claim 1 , wherein a method of forming the conductive via comprises:

forming a second patterned photoresist layer on the first patterned photoresist layer and covering the metallic wiring, wherein the second patterned photoresist layer comprises a second opening exposing a portion of the metallic wiring; and

forming the conductive via in the second opening and on the exposed portion of the metallic wiring.

3. The method as claimed in claim 2 , wherein the second patterned photoresist layer is removed during removing the first photoresist layer after forming the conductive via.

4. The method as claimed in claim 2 , wherein the second patterned photoresist layer is formed directly on the first patterned photoresist layer and the metallic wiring.

5. The method as claimed in claim 2 , wherein a material of the first patterned photoresist layer is different from a material of the second patterned photoresist layer.

6. The method as claimed in claim 2 , further comprising removing the seed layer not covered by the metallic wiring after removing the first patterned photoresist layer and the second patterned photoresist layer.

7. The method as claimed in claim 1 , further comprising laterally wrapping around the metallic wiring and the conductive via with an encapsulant.

8. The method as claimed in claim 7 , wherein laterally wrapping around the metallic wiring and the conductive via with the encapsulant comprises over-molding the metallic wiring and the conductive via followed by a grinding step.

9. The method as claimed in claim 1 , wherein the conductive via is formed directly on the metallic wiring without a seed layer formed therebetween.

10. A method, comprising:

providing a semiconductor die;

laterally encapsulating the semiconductor die with a first encapsulant;

forming redistribution sublayers including a dielectric layer and a metallic wiring over the semiconductor die and the first encapsulant;

forming a redistribution wiring on the dielectric layer and electrically connected to the metallic wiring;

forming a conductive via on the redistribution wiring;

forming a second encapsulant wrapping around the conductive via and the redistribution wiring; and

forming an under-ball metallurgy (UBM) pattern on the conductive via, wherein a lower surface of the UBM pattern is coplanar with upper surfaces of the second encapsulant and the conductive via.

11. The method as claimed in claim 10 , wherein a method of forming the redistribution wiring and the conductive via comprises:

forming a seed layer on the redistribution sublayers, wherein the seed layer extends continuously across the semiconductor die and covers the dielectric layer and the metallic wiring;

forming a first patterned photoresist layer having a first opening over the seed layer;

forming the redistribution wiring in the first opening and on the seed layer;

forming a second patterned photoresist layer having a second opening on the first patterned photoresist layer and the redistribution wiring;

forming the conductive via on the redistribution wiring and within the second opening; and

removing the first patterned photoresist layer and the second patterned photoresist layer.

12. The method as claimed in claim 11 , wherein the first patterned photoresist layer and the second patterned photoresist layer are removed in a single process.

13. The method as claimed in claim 11 , wherein the conductive via is formed directly on the redistribution wiring by plating using the seed layer as a plating seed layer without forming another seed layer between the conductive via and the redistribution wiring.

14. The method as claimed in claim 11 , wherein the second patterned photoresist layer is formed directly on the first patterned photoresist layer after forming the redistribution wiring, so that the second patterned photoresist layer is in contact with the first patterned photoresist layer and in contact with the redistribution wiring.

15. The method as claimed in claim 11 , wherein the first patterned photoresist layer is formed by spin-coating, and the second patterned photoresist layer is formed by dry film lamination.

16. The method as claimed in claim 10 , wherein a material of the second encapsulant is different from a material of the dielectric layer.

17. A semiconductor package, comprising:

a semiconductor die; and

a redistribution structure, disposed on the semiconductor die and electrically connected to the semiconductor die, the redistribution structure comprising:

redistribution sublayers including a dielectric layer and a metallic wiring; and

a redistribution wiring disposed on the dielectric layer and connected to the metallic wiring;

a plurality of conductive vias disposed on the redistribution wiring; and

an encapsulant laterally encapsulating the redistribution wiring and the conductive via; and

a plurality of under-ball metallurgy (UBM) patterns respectively disposed on the conductive vias, wherein a lower surface each of the UBM patterns is coplanar with upper surfaces of the encapsulant and the corresponding conductive via.

18. The semiconductor package as claimed in claim 17 , wherein the redistribution wiring is in physical contact with the conductive via.

19. The semiconductor package as claimed in claim 17 , wherein the redistribution structure further comprises a seed layer sandwiched between the dielectric layer and the redistribution wiring.

20. The semiconductor package as claimed in claim 17 , wherein a thickness of the metallic wiring is smaller than a thickness of the redistribution wiring or a thickness of the conductive via.