Efuse inside and gate structure on triple-well region
The present disclosure relates to semiconductor structures and, more particularly, to an eFuse and gate structure on a triple-well and methods of manufacture. The structure includes: a substrate comprising a bounded region; a gate structure formed within the bounded region; and an eFuse formed within the bounded region and electrically connected to the gate structure.
1. A structure comprising:
a substrate comprising a bounded region comprising a triple well region comprising a deep N-well, a P-well above the deep N-well and an N-well ring surrounding the deep P-well and above the deep N-well;
a gate structure formed directly over the P-well of the bounded region; and
an eFuse formed directly over the P-well of the bounded region and electrically connected to the gate structure.
2. The structure of claim 1 , wherein the N well ring surrounds the gate structure and the eFuse.
3. The structure of claim 2 , wherein the N-well ring contacts the deep N-well.
4. The structure of claim 2 , wherein the eFuse sits over a shallow trench isolation structure within the P-well and electrically connects to the gate structure by at least one metallization feature.
5. The structure of claim 4 , wherein the eFuse comprises a silicided polysilicon material.
6. The structure of claim 5 , wherein the gate structure comprises a field effect transistor and comprises a polysilicon gate structure.
7. The structure of claim 5 , further comprising a tie down diode within the triple-well region.
8. The structure of claim 1 , wherein the bounded region comprises an amorphous semiconductor layer buried in the substrate and the P-well extending through the amorphous semiconductor layer.
9. The structure of claim 8 , wherein the gate structure and the eFuse are above the amorphous semiconductor layer.
10. The structure of claim 9 , wherein the amorphous semiconductor layer comprises polysilicon material.
11. The structure of claim 10 , wherein the gate structure comprising a floating body field effect transistor.
12. A structure comprising:
a substrate comprising a region bounded by a well comprising a triple well region comprising a deep N-well, a P-well above the deep N-well and an N-well ring surrounding the P-well and above the deep N-well;
at least one shallow trench isolation structure within the region bounded by the well;
a gate structure directly over the P-well of the region bounded by the well; and
an eFuse electrically connecting to the gate structure and over the at least on shallow trench isolation structure, directly over the P-well of the region bounded.
13. The structure of claim 12 , further comprising a diffusion region in the region bounded by the well.
14. The structure of claim 13 , wherein the diffusion region comprises a tie down diode.
15. The structure of claim 12 , wherein the P-well is over the deep N-well and is surrounded by the N-well ring.
16. The structure of claim 15 , wherein the gate structure comprises parallel bit cells in the triple-well region.
17. The structure of claim 15 , further comprising shallow trench isolation structures at junctions of the triple-well region.
18. The structure of claim 12 , wherein the well comprises a P-well ring extending through a buried polysilicon material.
19. The structure of claim 18 , wherein the gate structure is a floating body gate structure.
20. A method comprising:
forming a bounded region in a substrate surrounded by a well comprising a triple well region comprising a deep N-well, a P-well above the deep N-well and an N-well ring surrounding the P-well and above the deep N-well;
forming at least one shallow trench isolation structure within the bounded region;
forming a gate structure directly over the P-well of the bounded region; and
forming an eFuse electrically connecting to the gate structure, the eFuse formed over the at least one shallow trench isolation structure, directly over the P-well of the bounded region.