IP Library › Granted Patent US 11,852,937
Granted Patent B2
US 11,852,937 · App. 17/863,575 · Granted Dec 26, 2023

Display device and method for manufacturing the display device

Inventors: Kenichi Okazaki (Tochigi, JP); Yukinori Shima (Tatebayashi, JP); Daisuke Kurosaki (Utsunomiya, JP); Masataka Nakada (Tochigi, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
G02F1/136286G02F1/1368
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Quick Facts
Patent No.
US 11,852,937
App. No.
17/863,575
Granted
Dec 26, 2023
Kind
B2
Abstract

The manufacturing yield of a display device is improved. The resistance of a display device to ESD is increased. The display device includes a substrate, a display portion, a connection terminal, a first wiring, and a second wiring. The first wiring is electrically connected to the connection terminal and includes a portion positioned between the connection terminal and the display portion. The second wiring is electrically connected to the connection terminal, is positioned between the connection terminal and an end portion of the substrate, and includes a portion in which a side surface is exposed at an end portion of the substrate. The display portion includes a transistor. The transistor includes a semiconductor layer, a gate insulating layer, and a gate electrode. The semiconductor layer and the second wiring include a metal oxide.

Claims (39)

1. A display device comprising a substrate, a display portion, a first wiring, and a second wiring,

wherein the display portion comprises a transistor,

wherein the transistor comprises a semiconductor layer, a gate insulating layer, and a gate electrode,

wherein the semiconductor layer at least comprises one metal element that is the same as the metal element included in the second wiring,

wherein the semiconductor layer comprises a first region overlapping with the gate electrode and a second region not overlapping with the gate electrode,

wherein the second wiring and the second region of the semiconductor layer are electrically connected by the first wiring, and

wherein a resistance of the second region and a resistance of the second wiring are lower than a resistance of the first region.

2. A display device comprising a substrate, a display portion, a first wiring, and a second wiring,

wherein the display portion comprises a transistor,

wherein the transistor comprises a semiconductor layer, a gate insulating layer, and a gate electrode,

wherein the semiconductor layer and the second wiring comprise the same metal oxide,

wherein the semiconductor layer comprises a first region overlapping with the gate electrode and a second region not overlapping with the gate electrode,

wherein the second wiring and the second region of the semiconductor layer are electrically connected by the first wiring, and

wherein a resistance of the second region and a resistance of the second wiring are lower than a resistance of the first region.

3. The display device according to claim 1 ,

wherein the semiconductor layer and the second wiring are provided on the same plane.

4. The display device according to claim 2 ,

wherein the semiconductor layer and the second wiring are provided on the same plane.

5. The display device according to claim 1 ,

wherein the resistance of the second wiring is higher than a resistance of the first wiring.

6. The display device according to claim 2 ,

wherein the resistance of the second wiring is higher than a resistance of the first wiring.

7. The display device according to claim 1 , further comprising:

a third wiring electrically connected to the transistor,

wherein the third wiring and the first wiring are provided on the same plane and comprise the same metal element.

8. The display device according to claim 2 , further comprising:

a third wiring electrically connected to the transistor,

wherein the third wiring and the first wiring are provided on the same plane and comprise the same metal element.

9. The display device according to claim 1 , further comprising an FPC, wherein the FPC comprises a portion covering an exposed end surface of the second wiring.

10. The display device according to claim 2 , further comprising an FPC, wherein the FPC comprises a portion covering an exposed end surface of the second wiring.

11. A method for manufacturing a display device comprising the steps of:

forming a transistor comprising a semiconductor layer over a substrate; and

forming a first wiring and a second wiring over the substrate;

wherein the semiconductor layer and the second wiring are formed by processing the same metal oxide film,

wherein the semiconductor layer comprises a first region overlapping with a gate electrode and a second region not overlapping with the gate electrode,

wherein the second wiring and the second region of the semiconductor layer are electrically connected by the first wiring, and

wherein a resistance of the second region and a resistance of the second wiring are lower than a resistance of the first region.

12. The method for manufacturing a display device according to claim 11 ,

wherein the semiconductor layer and the second wiring are provided on the same plane.

Priority Claims (1)
JP 2018-229400 · Dec 6, 2018 · national
Continuity (2)
Continuation 17291663
Related Publication 20220350213A1 · Nov 3, 2022