Performing hardware description language transformations

1. A method, comprising:

parsing hardware description language (HDL) code for an integrated circuit (IC) design to obtain an IC design parse tree;

parsing a transformation pattern to obtain a transformation pattern parse tree, the transformation pattern comprising a first pattern and a second pattern wherein the first pattern and the second pattern are specified using a language extension of the HDL;

using the IC design parse tree and the transformation pattern parse tree to identify a portion of the HDL code that matches the first pattern;

transforming, by a processor, the portion of the HDL code based on the second pattern to obtain a transformed portion of the HDL code; and

replacing the portion of the HDL code by the transformed portion of the HDL code.

2. The method of claim 1 , wherein the using the IC design parse tree and the transformation pattern parse tree to identify the portion of the HDL code that matches the first pattern comprises matching the transformation pattern parse tree with a portion of the IC design parse tree that corresponds to the portion of the HDL code.

3. The method of claim 1 , wherein the using the IC design parse tree and the transformation pattern parse tree to identify the portion of the HDL code that matches the first pattern comprises matching a property specified in the first pattern with a property of the portion of the HDL code.

4. The method of claim 1 , wherein the IC design parse tree and the transformation pattern parse tree are maintained separately.

5. The method of claim 1 , wherein the transformation pattern comprises one or more of an expression pattern, a statement pattern, and a statement block pattern.

6. The method of claim 1 , further comprising simulating the IC design using the transformed portion of the HDL code.

7. A non-transitory storage medium storing instructions, which when executed by a processor, cause the processor to:

parse hardware description language (HDL) code for an integrated circuit (IC) design to obtain an IC design parse tree;

parse a transformation pattern to obtain a transformation pattern parse tree, the transformation pattern comprising a first pattern and a second pattern, wherein the first pattern and the second pattern are specified using a language extension of the HDL;

use the IC design parse tree and the transformation pattern parse tree to identify a portion of the HDL code that matches the first pattern;

transform the portion of the HDL code based on the second pattern to obtain a transformed portion of the HDL code; and

replace the portion of the HDL code by the transformed portion of the HDL code.

8. The non-transitory storage medium of claim 7 , wherein the using the IC design parse tree and the transformation pattern parse tree to identify the portion of the HDL code that matches the first pattern comprises matching the transformation pattern parse tree with a portion of the IC design parse tree that corresponds to the portion of the HDL code.

9. The non-transitory storage medium of claim 7 , wherein the using the IC design parse tree and the transformation pattern parse tree to identify the portion of the HDL code that matches the first pattern comprises matching a property specified in the first pattern with a property of the portion of the HDL code.

10. The non-transitory storage medium of claim 7 , wherein the IC design parse tree and the transformation pattern parse tree are maintained separately.

11. The non-transitory storage medium of claim 7 , wherein the transformation pattern comprises one or more expression patterns, one or more statement patterns, one or more statement block patterns, or a combination thereof.

12. The non-transitory storage medium of claim 7 , wherein the instructions, which when executed by the processor, cause the processor to simulate the IC design using the transformed portion of the HDL code.

13. A system comprising:

a memory storing instructions; and

a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor to:

parse hardware description language (HDL) code for an integrated circuit (IC) design to obtain an IC design parse tree;

parse a transformation pattern to obtain a transformation pattern parse tree, the transformation pattern comprising a first pattern and a second pattern, wherein the first pattern and the second pattern are specified using a language extension of the HDL;

use the IC design parse tree and the transformation pattern parse tree to identify a portion of the HDL code that matches the first pattern;

transform the portion of the HDL code based on the second pattern to obtain a transformed portion of the HDL code; and

replace the portion of the HDL code by the transformed portion of the HDL code.

14. The system of claim 13 , wherein the using the IC design parse tree and the transformation pattern parse tree to identify the portion of the HDL code that matches the first pattern comprises matching the transformation pattern parse tree with a portion of the IC design parse tree that corresponds to the portion of the HDL code.

15. The system of claim 13 , wherein the using the IC design parse tree and the transformation pattern parse tree to identify the portion of the HDL code that matches the first pattern comprises matching a property specified in the first pattern with a property of the portion of the HDL code.

16. The system of claim 13 , wherein the IC design parse tree and the transformation pattern parse tree are maintained separately.

17. The system of claim 13 , wherein the transformation pattern comprises one or more expression patterns, one or more statement patterns, one or more statement block patterns, or a combination thereof.