Methods of designing and fabricating a semiconductor device based on determining a least common multiple between select layout pitches

1. A method of designing a semiconductor device, the method comprising:

performing a simulation a number of times, the simulation including,

holding a gate pitch of a plurality of gate wiring patterns constant,

varying a first pitch of first wiring patterns of a plurality of first-direction wiring patterns that extend in a first direction,

varying a second pitch of second wiring patterns of the plurality of first-direction wiring patterns that extend in the first direction, and

varying a third pitch of third wiring patterns of the plurality of first-direction wiring patterns that extend in the first direction;

for each of the number of times, calculating a calculated least common multiple of the gate pitch, the first pitch, the second pitch, and the third pitch;

determining a determined least common multiple from among the calculated least common multiples; and

designing a plurality of layers based on the determined least common multiple.

2. The method of claim 1 , further comprising:

performing an optical proximity correction on the plurality of layers; and

manufacturing a plurality of photomasks based on the optical proximity correction of each of the plurality of layers.

3. A method of fabricating a semiconductor device comprising:

using the plurality of photomasks of claim 2 in a plurality of exposure and etching processes.

4. The method of claim 3 , wherein the using the plurality of photomasks comprises:

performing a gate exposure and etch process on a substrate to form a plurality of gate wiring lines using a gate photomask that includes the plurality of gate wiring patterns;

subsequently, performing a first exposure and etch process on the substrate to form a plurality of first wiring lines using a first photomask that includes the plurality of first wiring patterns;

subsequently, performing a second exposure and etch process on the substrate to form a plurality of second wiring lines using a second photomask that includes the plurality of second wiring patterns; and

subsequently, performing a third exposure and etch process on the substrate to form a plurality of third wiring lines using a third photomask that includes the plurality of third wiring patterns.

5. The method of claim 4 , further comprising, after the performing the gate exposure and etch process and before the performing the first exposure and etch process:

performing a fourth exposure and etch process to form a first power line, a plurality of fourth wiring lines, and a second power line, wherein

the first power line, the plurality of fourth wiring lines, and the second power line extending in a second direction crossing the first direction,

the first power line, the plurality of fourth wiring lines, and the second power line at a same level of the semiconductor device.

6. A method of fabricating a semiconductor device, the method including:

performing a high-level design of the semiconductor device to generate a netlist of the semiconductor device;

designing a plurality of first-direction layouts of the semiconductor device based on the netlist;

performing optical proximity corrections on the plurality of first-direction layouts;

generating a plurality of photomasks based on the optical proximity correction; and

fabricating the semiconductor device based on the plurality of photomasks, wherein

the designing the plurality of first-direction layouts includes repeating a simulation a number of times, the simulation including,

holding a first pitch of a first one of the plurality of first-direction layouts constant,

varying other pitches of other ones of the plurality of first-direction layouts, and

calculating a least common multiple of the first pitch and each of the other pitches.

7. The method of claim 6 , wherein the first pitch corresponds to a gate pitch.

8. The method of claim 6 , further comprising:

designing a plurality of second-direction layouts of the semiconductor device based on the netlist, wherein

the designing the plurality of second-direction layouts includes repeating a second simulation a number of times, the second simulation including,

holding a second pitch of a second one of the plurality of second-direction layouts constant,

varying other pitches of other ones of the plurality of second-direction layouts, and

calculating a second least common multiple of the second pitch and each of the other pitches.