Power semiconductor device
A power semiconductor device includes a P-type substrate, an N-type well region, a P-type body region, a gate oxide layer, a polysilicon gate, a first oxide layer, a first N+ contact region, a first P+ contact region, drain metal, a first-type doped region, and a gate oxide layer. An end of the P-type body region is flush with or exceeds an end of the polysilicon gate, wherein C gd of the power semiconductor device is reduced and a switching frequency of the power semiconductor device is increased. A polysilicon field plate connected with a source is introduced over a drift region that is not only shield an influence of the polysilicon gate on the drift region, thereby eliminating C gd caused by overlapping of traditional polysilicon gate and drift region, but also enable the power semiconductor device to have strong robustness against an hot carrier effect.
1. A power semiconductor device, comprising: a P-type substrate, an N-type well region located over the P-type substrate, a P-type body region located on a left side surface of the N-type well region, wherein
a first N+ contact region and a first P+ contact region are adjacent and both located on a surface of the P-type body region,
an another first N+ contact region is located on a right side surface of the N-type well region,
a gate oxide layer is located over the P-type body region and the N-type well region,
a polysilicon gate is located on an upper surface of the gate oxide layer,
a first oxide layer is located on a surface of the N-type well region, the first N+ contact region and the first P+ contact region are shorted through a source metal,
a drain metal is connected to the first N+ contact region on the right side surface of the N-type well region,
a first-type doped region is located on the surface of the N-type well region and below the gate oxide layer, and
a polysilicon field plate is located over the gate oxide layer between the P-type body region and the first oxide layer: the polysilicon field plate is shorted with the first N+ contact region and the first P+ contact region through the source metal: the polysilicon field plate is separated from silicon gate by a space on the upper surface of the gate oxide layer.
2. The power semiconductor device according to claim 1 , wherein a right boundary of the P-type body region is flush with a right boundary of the polysilicon gate or exceeds the right boundary of the polysilicon gate.
3. The power semiconductor device according to claim 1 , wherein the source metal is directly connected with the gate oxide layer.
4. The power semiconductor device according to claim 1 . wherein the first-type doped region is formed jointly by multiple implantations.
5. The power semiconductor device according to claim 1 , wherein the first-type doped region is formed by multiple ion implantations with different energies and doses.
6. The power semiconductor device according to claim 1 . wherein the first-type doped region comprises a separated first-type doped region formed by two implantations, and a second-type doped region is implanted in a middle of the separated first-type doped region.
7. The power semiconductor device according to claim 6 , wherein another first-type doped region is implanted over the first-type doped region formed by the two implantations and the second-type doped region.
8. The power semiconductor device according to claim 5 , wherein a P-type well region is implanted on a right side of the first-type doped region, and the first P+ contact region is implanted inside the P-type well region; the first N+ contact region and the first P+ contact region located within the P-type body region are shorted with the first P+ contact region located in the P-type well region through the source metal.
9. The power semiconductor device according to claim 1 , wherein a polysilicon field plate is located over the gate oxide layer; the polysilicon field plate is shorted with the first N+ contact region and the first P+ contact region through the source metal.
10. The power semiconductor device according to claim 5 , wherein a first buried layer is added inside the P-type body region and below the first N+ contact region and the first P+ contact region.
11. The power semiconductor device according to claim 5 , wherein a first polysilicon field plate is provided over the gate oxide layer between the P-type body region and the first oxide layer, and a second polysilicon. field plate is provided over the first oxide layer, the first polysilicon field plate and the first polysilicon field plate are shorted with the first N+ contact region and the first P+ contact region through the source metal.
12. The power semiconductor device according to claim 5 , wherein a first type drift region inject is provided on a right side of the first-type doped region and below the first oxide layer.
13. The power semiconductor device according to claim 1 , wherein the P-type substrate is a bulk silicon substrate or an SOI substrate.
14. The power semiconductor device according to claim 1 , wherein a right boundary of the P-type body region is flush with a right boundary of the polysilicon gate or exceeds the right boundary of the polysilicon gate.
15. The power semiconductor device according to claim 1 , wherein the first-type doped region is formed jointly by multiple implantations.
16. The power semiconductor device according to claim 7 , wherein a P-type well region is implanted on a right side of the first-type doped region, and the first P+ contact region is implanted inside the P-type well region; the first N+ contact region and the first P+ contact region located within the P-type body region are shorted with the first P+ contact region located in the P-type well region through the source metal.
17. The power semiconductor device according to claim 2 , wherein the P-type substrate is a bulk silicon substrate or an SOT substrate.
18. The power semiconductor device according to claim 3 , wherein the P-type substrate is a bulk silicon substrate or an SOT substrate.