Semiconductor device
A semiconductor device including a substrate that includes first to third regions; a first channel structure on the first region and including first channel patterns that are vertically stacked on the substrate; a second channel structure on the second region and including a second channel pattern on the substrate; a third channel structure on the third region and including third channel patterns and fourth channel patterns that are vertically and alternately stacked on the substrate; first to third gate electrodes on the first to third channel structures; and first to third source/drain patterns on opposite sides of the first to third channel structures, wherein the first, second, and fourth channel patterns include a first semiconductor material, and the third channel patterns include a second semiconductor material different from the first semiconductor material.
1. A semiconductor device, comprising:
a substrate that includes a first region, a second region, and a third region;
a first channel structure on the first region, the first channel structure including a plurality of first channel patterns that are vertically stacked on the substrate;
a second channel structure on the second region, the second channel structure including a second channel pattern on the substrate;
a third channel structure on the third region, the third channel structure including a plurality of third channel patterns and a plurality of fourth channel patterns that are vertically and alternately stacked on the substrate;
a first gate electrode on the first channel structure, a second gate electrode on the second channel structure, and a third gate electrode on the third channel structure; and
a first source/drain pattern on opposite sides of the first channel structure, a second source/drain pattern on opposite sides of the second channel structure, and a third source/drain pattern on opposite sides of the third channel structure,
wherein:
the plurality of first channel patterns, the second channel pattern, and the plurality of fourth channel patterns each include a first semiconductor material, and
the plurality of third channel patterns include a second semiconductor material different from the first semiconductor material.
2. The semiconductor device as claimed in claim 1 , wherein the plurality of first channel patterns are at a level substantially the same as a level of the plurality of fourth channel patterns.
3. The semiconductor device as claimed in claim 1 , wherein the first gate electrode extends across the first channel structure and surrounds each first channel pattern of the plurality of first channel patterns.
4. The semiconductor device as claimed in claim 1 , further comprising a first dielectric layer between the first gate electrode and the first channel structure, a second dielectric layer between the second gate electrode and the second channel structure, and a third gate dielectric layer between the third gate electrode and the third channel structure,
wherein the first gate dielectric layer conformally covers a surface of each first channel pattern of the plurality of first channel patterns.
5. The semiconductor device as claimed in claim 4 , wherein:
the third gate dielectric layer conformally covers a surface of the third channel structure, and
the third gate dielectric layer is in contact with sidewalls of the plurality of third channel patterns and sidewalls of the plurality of fourth channel patterns.
6. The semiconductor device as claimed in claim 1 , wherein
the second gate electrode extends across the second channel structure and covers opposite sidewalls of the second channel pattern, and
the third gate electrode extends across the third channel structure and covers opposite sidewalls of the plurality of third channel patterns and opposite sidewalls of the plurality of fourth channel patterns.
7. The semiconductor device as claimed in claim 1 , wherein the first semiconductor material and the second semiconductor material each independently include silicon, germanium, silicon-germanium, or a group compound semi conductor.
8. The semiconductor device as claimed in claim 1 , wherein:
the first semiconductor material includes silicon, and
the second semiconductor material includes silicon-germanium.
9. A semiconductor device, comprising:
a substrate that includes a first region, a second region, and a third region;
a first channel structure on the first region, the first channel structure including a plurality of first channel patterns that are vertically stacked on the substrate;
a second channel structure on the second region, the second channel structure including a second channel pattern on the substrate;
a third channel structure on the third region, the third channel structure including a plurality of third channel patterns and a plurality of fourth channel patterns that are vertically and alternately stacked on the substrate;
a first gate electrode on the first channel structure, a second gate electrode on the second channel structure, and a third gate electrode on the third channel structure;
a first dielectric layer between the first gate electrode and the first channel structure, a second dielectric layer between the second gate electrode and the second channel structure, and a third gate dielectric layer between the third gate electrode and the third channel structure; and
a first source/drain pattern on opposite sides of the first channel structure, a second source/drain pattern on opposite sides of the second channel structure, and a third source/drain pattern on opposite sides of the third channel structure,
wherein:
the third channel structure has an uneven sidewall, and
the third gate dielectric layer covers the uneven sidewall.
10. The semiconductor device as claimed in claim 9 , wherein sidewalls of the plurality of third channel patterns are laterally recessed to a greater depth than a depth to which sidewalls of the plurality of fourth channel patterns are laterally recessed.
11. The semiconductor device as claimed in claim 9 , wherein each third channel pattern of the plurality of third channel patterns has a rounded sidewall.
12. The semiconductor device as claimed in claim 9 , wherein the third gate dielectric layer conformally covers a surface of the third channel structure and contacts sidewalls of the plurality of third channel patterns and sidewalls of the plurality of fourth channel patterns.
13. The semiconductor device as claimed in claim 9 , wherein the first gate electrode extends across the first channel structure and surrounds each first channel pattern of the plurality of first channel patterns.
14. The semiconductor device as claimed in claim 9 , wherein the first gate dielectric layer conformally covers a surface of each first channel pattern of the plurality of first channel patterns.
15. A semiconductor device, comprising:
a substrate that includes a first region, a second region, and a third region;
a first channel structure on the first region, the first channel structure including a plurality of first channel patterns that are vertically stacked on the substrate;
a second channel structure on the second region, the second channel structure including a second channel pattern on the substrate;
a third channel structure on the third region, the third channel structure having an uneven sidewall and including a plurality of third channel patterns and a plurality of fourth channel patterns that are vertically and alternately stacked on the substrate;
a first gate electrode on the first channel structure, a second gate electrode on the second channel structure, and a third gate electrode on the third channel structure;
a first dielectric layer between the first gate electrode and the first channel structure, a second dielectric layer between the second gate electrode and the second channel structure, and a third gate dielectric layer between the third gate electrode and the third channel structure; and
a first source/drain pattern on opposite sides of the first channel structure, a second source/drain pattern on opposite sides of the second channel structure, and a third source/drain pattern on opposite sides of the third channel structure,
wherein:
the plurality of first channel patterns, the second channel pattern, and the plurality of fourth channel patterns each include silicon, and
the plurality of third channel patterns each include silicon-germanium.
16. The semiconductor device as claimed in claim 15 , wherein sidewalls of the plurality of third channel patterns are laterally recessed to a greater depth than a depth to which sidewalls of the plurality of fourth channel patterns are laterally recessed.
17. The semiconductor device as claimed in claim 15 , wherein each third channel pattern of the plurality of third channel patterns has a rounded sidewall.
18. The semiconductor device as claimed in claim 15 , wherein the first gate electrode extends across the first channel structure and surrounds each first channel pattern of the plurality of first channel patterns.
19. The semiconductor device as claimed in claim 18 , wherein the first gate dielectric layer conformally covers a surface of each first channel pattern of the plurality of first channel patterns.
20. The semiconductor device as claimed in claim 15 , wherein:
the second gate electrode extends across the second channel structure and covers opposite sidewalls of the second channel pattern, and
the third gate electrode extends across the third channel structure and covers opposite sidewalls of the plurality of third channel patterns and sidewalls of the plurality of fourth channel patterns.