Time domains synchronization in a system on chip

1. A method for synchronizing a first time domain of a first device with a second time domain of a second device, the method comprising:

detecting at least one periodic trigger event generated in at least one trigger time domain selected from the first time domain, the second time domain, and a third time domain of a third device;

acquiring, at instants of detecting the at least one periodic trigger event, current timestamp values representing instantaneous states of the first time domain, the second time domain, and the third time domain, other than the at least one trigger time domain;

determining respective lapses of time in the first, second and third time domains based on the at least one periodic trigger event and the current timestamp values;

comparing, in the third time domain, at least two of the respective lapses of time; and

adjusting, based on the comparing, a frequency of a second clock of the second time domain to synchronize the second clock with a first clock of the first time domain.

2. The method according to claim 1 , further comprising adjusting, based on the comparing, a phase of the second clock of the second time domain.

3. The method according to claim 1 , wherein acquiring the current timestamp values is performed at same instants of detecting a same periodic trigger event, or at different instants of detecting different periodic trigger events.

4. The method according to claim 1 , wherein the first time domain is defined by a precision time measurement protocol “PTM” of a peripheral component interconnect express “PCIe” interface, the second time domain is defined by a precision time protocol “PTP” of a network interface “Ethernet,” and the third time domain is clocked by a free running local clock configured to clock software operations.

5. The method according to claim 1 , wherein the at least one trigger time domain comprises the first time domain, and the at least one periodic trigger event generated in the first time domain occurs in response to a condition being verified on a transition of at least one bit of a current timestamp value representing the instantaneous state of the first time domain, each bit of the current timestamp value being communicated on a dedicated channel of a timestamp bus.

6. The method according to claim 1 , wherein the at least one trigger time domain does not comprise the first time domain, each bit of the current timestamp value representing the instantaneous state of the first time domain being communicated on a dedicated channel of a timestamp bus, and the acquiring the current timestamp value representing the instantaneous state of the first time domain comprises loading a latch with bits present on each channel of the timestamp bus, the loading the latch being controlled at the instants of detecting the at least one periodic trigger event.

7. The method according to claim 1 , wherein the at least one trigger time domain comprises the second time domain, and the at least one periodic trigger event generated in the second time domain is detected in response to a periodic signal being generated in the second time domain.

8. A system comprising:

a first device comprising a first counter configured to provide a current timestamp value representing an instantaneous state of a first time domain;

a second device comprising a second counter configured to provide a current timestamp value representing an instantaneous state of a second time domain; and

a third device comprising:

a local clock generator configured to clock a third time domain; and

a synchronization module configured to:

detect at least one periodic trigger event generated in at least one trigger time domain selected from the first time domain, the second time domain and the third time domain;

acquire, at instants of detection of the at least periodic one trigger event, the current timestamp values representing the first time domain, the second time domain and the third time domain, other than the at least one trigger time domain;

determine respective lapses of time in the first, second and third time domains based on the at least one periodic trigger event and the current timestamp values;

compare at least two of the respective lapses of time; and

generate, based on the compare, a control configured to adjust a frequency of a second clock of the second time domain to synchronize the second clock with a first clock of the first time domain.

9. The system according to claim 8 , wherein the synchronization module is configured to adjust, based on the comparing, a phase of the second clock of the second time domain.

10. The system according to claim 8 , wherein the synchronization module is configured to acquire the current timestamp values at same instants of detecting a same periodic trigger event, or at different instants of detecting different periodic trigger events.

11. The system according to claim 8 , wherein the first device comprises a peripheral component interconnect express “PCIe” interface configured to define the first time domain by a precision time measurement “PTM” protocol, the second device comprises a network interface “Ethernet” configured to define the second time domain by a precision time protocol “PTP,” and the local clock generator of the third device is configured to clock software operations.

12. The system according to claim 8 , wherein the at least one trigger time domain comprises the first time domain, the first counter being configured to communicate each bit of the current timestamp value on a dedicated channel of a timestamp bus, and wherein the synchronization module is configured to detect the at least one periodic trigger event generated in the first time domain in response to a condition being verified on a transition of at least one bit on the respective channel of the timestamp bus.

13. The system according to claim 8 , wherein the at least one trigger time domain does not comprise the first time domain, the first counter being configured to communicate each bit of the current timestamp value on a dedicated channel of a timestamp bus, and wherein the synchronization module comprises a latch on the timestamp bus and is configured to acquire the current timestamp value representing the instantaneous state of the first time domain by controlling loading of the latch, at the instants of the at least one periodic trigger event, with bits present on each channel of the timestamp bus.

14. The system according to claim 8 , wherein the at least one trigger time domain comprises the second time domain, and the synchronization module is configured to detect the at least one periodic trigger event generated in the second time domain, in response to a periodic signal being generated in the second time domain.

15. A system on chip comprising:

a peripheral component interconnect express “PCIe” device comprising a first counter configured to provide a current timestamp value representing an instantaneous state of a first time domain;

an Ethernet device comprising a second counter configured to provide a current timestamp value representing an instantaneous state of a second time domain; and

a central processing unit “CPU” device comprising:

a local clock generator configured to clock a third time domain; and

a synchronization module configured to:

detect at least one periodic trigger event generated in at least one trigger time domain selected from the first time domain, the second time domain and the third time domain;

acquire, at instants of detection of the at least periodic one trigger event, the current timestamp values representing the first time domain, the second time domain and the third time domain, other than the at least one trigger time domain;

determine respective lapses of time in the first, second and third time domains based on the at least one periodic trigger event and the current timestamp values;

compare at least two of the respective lapses of time; and

generate, based on the compare, a control configured to adjust a frequency of a second clock of the second time domain to synchronize the second clock with a first clock of the first time domain.

16. The system on chip according to claim 15 , wherein the synchronization module is configured to adjust, based on the comparing, a phase of the second clock of the second time domain.

17. The system on chip according to claim 15 , wherein the synchronization module is configured to acquire the current timestamp values at same instants of detecting a same periodic trigger event, or at different instants of detecting different periodic trigger events.

18. The system on chip according to claim 15 , wherein the at least one trigger time domain comprises the first time domain, the first counter being configured to communicate each bit of the current timestamp value on a dedicated channel of a timestamp bus, and wherein the synchronization module is configured to detect the at least one periodic trigger event generated in the first time domain in response to a condition being verified on a transition of at least one bit on the respective channel of the timestamp bus.

19. The system on chip according to claim 15 , wherein the at least one trigger time domain does not comprise the first time domain, the first counter being configured to communicate each bit of the current timestamp value on a dedicated channel of a timestamp bus, and wherein the synchronization module comprises a latch on the timestamp bus and is configured to acquire the current timestamp value representing the instantaneous state of the first time domain by controlling loading of the latch, at the instants of the at least one periodic trigger event, with bits present on each channel of the timestamp bus.

20. The system on chip according to claim 15 , wherein the at least one trigger time domain comprises the second time domain, and the synchronization module is configured to detect the at least one periodic trigger event generated in the second time domain, in response to a periodic signal being generated in the second time domain.