Semiconductor memory devices with different doping types

1. A semiconductor device, comprising:

a plurality of first nanostructures vertically separated from one another;

a first gate structure wrapping around each of the plurality of first nanostructures;

a plurality of second nanostructures vertically separated from one another;

a second gate structure wrapping around each of the plurality of second nanostructures;

a first drain/source structure coupled to a first end of each of the first nanostructures;

a second drain/source structure coupled to both of a second end of each of the first nanostructures and a first end of each of the second nanostructures; and

a third drain/source structure coupled to a second end of each of the second nanostructures;

wherein the first drain/source structure has a first doping type, the second and third drain/source structures have a second doping type, and the first doping type is opposite to the second doping type.

2. The semiconductor device of claim 1 , wherein each of the first nanostructures includes a first portion with a higher concentration of the first doping type and a second portion with a lower concentration of the first doping type, and each of the second nanostructure is with the first doping type.

3. The semiconductor device of claim 2 , wherein the first portion is located closer to the first drain/source structure than to the second drain/source structure, and the second portion is located closer to the second drain/source structure than to the first drain/source structure.

4. The semiconductor device of claim 2 , wherein a ratio of the first portion to the second portion is about 1.

5. The semiconductor device of claim 2 , wherein a ratio of the first portion to the second portion is less than or greater than 1.

6. The semiconductor device of claim 1 , wherein the first doping type is a p-type, and the second doping type is an n-type.

7. The semiconductor device of claim 1 , wherein the first gate structure includes a first gate dielectric and a first gate metal, and the second gate structure includes a second gate dielectric and a second gate metal.

8. The semiconductor device of claim 7 , wherein at least a portion of the first gate dielectric is broken down to form a resistor across the first gate structure and the second drain/source structure.

9. The semiconductor device of claim 1 , wherein the first drain/source structure is floating and the third drain/source structure is operatively connected to a bit line, with the first gate structure and second gate structure connected to a programming word line and a reading word line, respectively.

10. A memory device, comprising:

a plurality of memory cells, wherein each of the memory cells has a first transistor and a second transistor coupled to each other in series;

a first access line operatively coupled to a respective gate of each of the first transistors; and

a second access line operatively coupled to a respective gate of each of the second transistors;

wherein each of the first transistors has a first drain terminal and a first source terminal and each of the second transistors has a second drain terminal and a second source terminal; and

wherein the first drain terminals have a first conduction type, and the first source terminals, the second drain terminals, and the second source terminals have a second conduction type opposite to the first conduction type,

wherein the first access line includes a first word line that programs each of the memory cells, and the second access line includes a second word line that reads each of the memory cells, wherein the first word line provides a breakdown voltage to convert at least one of the first transistors to a resistor.

11. The memory device of claim 10 , wherein the first drain terminals are each floating.

12. The memory device of claim 10 , wherein the second source terminals are connected to respective bit lines.

13. The memory device of claim 10 , wherein the first conduction type is a p-type, and the second conduction type is an n-type.

14. The memory device of claim 10 , wherein each of the first transistors has a first channel operating as a combination of a p-type and an n-type, and each of the second transistors has a second channel operating as the n-type.

15. The memory device of claim 14 , wherein the first channel includes a plurality of first nanosheets coupled between the first source terminal and the first drain terminal, and the second channel includes a plurality of second nanosheets coupled between the second source terminal and the second drain terminal.

16. A method for operating a memory device, comprising:

forming a first transistor having a first gate terminal, a first source terminal, and a first drain terminal, wherein the first drain terminal has a first conduction type and the first source terminal has a second conduction type opposite to the first conduction type;

forming a second transistor having a second gate terminal, a second source terminal, and a second drain terminal, wherein the second drain terminal and the second source terminal have the second conduction type;

floating the first drain terminal, connecting the first source terminal to the second drain terminal, and connecting the second source terminal to a bit line; and

applying a voltage on the first gate terminal to form a resistor across the first gate terminal and the first source terminal.

17. The method of claim 16 , wherein the first conduction type is a p-type, and the second conduction type is an n-type.

18. The method of claim 16 , wherein the first transistor has a first channel operating as a combination of a p-type and an n-type, and the second transistor has a second channel operating as the n-type.