IP Library › Granted Patent US 11,856,827
Granted Patent B2
US 11,856,827 · App. 17/428,543 · Granted Dec 26, 2023

Display device with reduced leakage current

Inventors: Tamotsu Sakai (Sakai, JP); Tetsuya Ueno (Sakai, JP)
Assignee: SHARP KABUSHIKI KAISHA
H10K59/131
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Quick Facts
Patent No.
US 11,856,827
App. No.
17/428,543
Granted
Dec 26, 2023
Kind
B2
Abstract

A display device includes: a semiconductor layer; a gate insulating film; a first display wire; a first interlayer insulating film; a second display wire; a second interlayer insulating film; and a third display wire stacked on a substrate in this order, pixel circuits being provided corresponding to intersections of data signal lines and scanning signal lines included in the third display wire, each of the pixel circuits including a first transistor and a second transistor in which any one of the scanning signal lines overlaps the semiconductor layer through the gate insulating film, one terminal of the first transistor and one terminal of the second transistor are connected together through a connector included in a conductor region of the semiconductor layer, and the connector includes an overlap connector overlapped in a plan view with the data signal lines through a constant potential wires included in the first display wire.

Claims (36)

1. A display device displaying an image by supplying corresponding data signals to a plurality of pixel circuits arranged in a display panel, the display device comprising:

a semiconductor layer; a gate insulating film; a first display wire; a first interlayer insulating film; a second display wire; a second interlayer insulating film; and a third display wire stacked on a substrate in this order,

the first display wire including a plurality of scanning signal lines extending in a row direction,

the second display wire including a plurality of constant potential wires extending in the row direction,

the third display wire including a plurality of data signal lines extending in a column direction and intersecting with the scanning signal lines and the constant potential wires, the column direction intersecting with the row direction,

the plurality of pixel circuits provided corresponding to intersections of the data signal lines and the scanning signal lines,

each of the pixel circuits including a first transistor and a second transistor in which any one of the scanning signal lines overlaps the semiconductor layer on top of the gate insulating film,

one conductive terminal of the first transistor and one conductive terminal of the second transistor being connected together through a connector included in a conductor region of the semiconductor layer, and

the connector including an overlap connector overlapped in a plan view with the data signal lines through the constant potential wires.

2. The display device according to claim 1 , wherein

the one conductive terminal and another conductive terminal of the first transistor are arranged in the column direction along the data signal lines,

the one conductive terminal and another conductive terminal of the second transistor are arranged in the column direction along the data signal lines, and

the overlap connector overlaps with the constant potential wires, and extends in the row direction.

3. The display device according to claim 1 , wherein

any one of the constant potential wires is an initialization wire.

4. The display device according to claim 3 , wherein

the first transistor and the second transistor serve as an initialization transistor.

5. The display device according to claim 4 , wherein

each of the pixel circuits includes a drive transistor,

another conductive terminal of the first transistor is electrically connected to the initialization wire, and

another conductive terminal of the second transistor is electrically connected to a control terminal of the drive transistor.

6. The display device according to claim 1 , wherein:

each of the pixel circuits further includes a third transistor in which a branch gate electrode overlaps the semiconductor layer, the branch gate electrode, branching off the scanning signal lines, overlapping the first transistor and the second transistor, and extending.

7. The display device according to claim 6 , wherein

the third transistor includes: one conductive terminal connected to the one conductive terminal of the first transistor through the connector; and another conductive terminal connected to the one conductive terminal of the second transistor through the connector.

8. The display device according to claim 6 , wherein

the semiconductor layer including the third transistor overlaps the constant potential wires in a plan view.

9. The display device according to claim 6 , wherein:

the data signal lines pass between the first transistor and the third transistor in the row direction.

10. The display device according to claim 6 , wherein

the third display wire further includes a power-source voltage line, and

the power-source voltage line passes between the second transistor and the third transistor in the row direction.

11. The display device according to claim 1 , wherein

another conductive terminal of the first transistor is connected to any one of conductive terminals of an initialization transistor of a neighboring pixel circuit through the conductor region of the semiconductor layer.

12. The display device according to claim 1 , wherein

the scanning signal lines include a light-emission control line.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 4, 2021
From: SAKAI, TAMOTSU; UENO, TETSUYA
To: SHARP KABUSHIKI KAISHA
Reel/Frame 057082/0340 →
Continuity (1)
Related Publication 20220181425A1 · Jun 9, 2022