IP Library › Granted Patent US 11,861,191
Granted Patent B2
US 11,861,191 · App. 17/500,676 · Granted Jan 2, 2024

Parameter table protection for a memory system

Inventor: Binbin Huo (Taufkirchen, DE)
Assignee: Micron Technology, Inc.
G06F3/0632G06F3/0604G06F3/0679
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Quick Facts
Patent No.
US 11,861,191
App. No.
17/500,676
Granted
Jan 2, 2024
Kind
B2
Abstract

Methods, systems, and devices for parameter table protection for a memory system are described. Upon booting a memory system for a first time, the memory system or a host system may generate an error control code associated with parameter data stored to the memory system. The error control code may be stored to the memory system and may be configured to correct one or more errors in the parameter data upon subsequent boot sequences of the memory system. Accordingly, upon booting the memory system for a second or a subsequent time, the error control code may be used to identify and correct errors in the parameter data, which may reduce the quantity of copies of parameter data stored to the memory system and may prevent the memory system from experiencing a system crash.

Claims (78)

1. A method, comprising:

identifying, upon booting a memory system for a first occurrence, parameter data for operating the memory system stored to a non-volatile memory device of the memory system;

generating, at the memory system, a first error control code associated with the parameter data based at least in part on identifying the parameter data stored to the non-volatile memory device of the memory system, the first error control code for correcting a first quantity of errors;

identifying, upon booting the memory system for a second occurrence, a first error associated with the parameter data using the first error control code;

correcting, at the memory system, the first error associated with the parameter data based at least in part on identifying the first error; and

generating, at the memory system, a second error control code associated with the parameter data based at least in part on correcting the parameter data, the second error control code for correcting a second quantity of errors different than the first quantity of errors.

2. The method of claim 1 , further comprising:

incrementing a counter based at least in part on correcting the first error associated with the parameter data, wherein a value of the counter is associated with a quantity of corrected errors of the parameter data.

3. The method of claim 2 , further comprising:

comparing the value of the counter to a threshold value associated with the first error control code based at least in part on incrementing the counter, wherein correcting the first error associated with the parameter data is based at least in part on the value of the counter failing to satisfy the threshold value.

4. The method of claim 3 , wherein the threshold value is based at least in part on the first quantity of errors that are correctable by the first error control code.

5. The method of claim 2 , further comprising:

identifying, upon booting the memory system for a third occurrence, a second error associated with the parameter data using the first error control code;

incrementing the counter based at least in part on identifying the second error associated with the parameter data; and

correcting, at the memory system, the second error associated with the parameter data based at least in part on identifying the second error associated with the parameter data and incrementing the counter.

6. The method of claim 5 , further comprising:

determining that the value of the counter satisfies a threshold value associated with the first quantity of errors correctable by the first error control code based at least in part on incrementing the counter; and

selecting the second error control code based at least in part on determining that the value of the counter satisfies the threshold value, wherein the second quantity of errors is greater than the threshold value.

7. The method of claim 6 , further comprising:

increasing the threshold value based at least in part on selecting the second error control code for correcting the second quantity of errors associated with the parameter data.

8. The method of claim 5 , further comprising:

determining that the value of the counter is above a first threshold value associated with the first quantity of errors correctable by the first error control code and below a second threshold value associated with a third quantity of errors correctable by the first error control code based at least in part on incrementing the counter; and

selecting the second error control code based at least in part on determining that the value of the counter is above the first threshold value and below the second threshold value, wherein the second quantity of errors is greater than the first threshold value.

9. The method of claim 2 , further comprising:

determining that the value of the counter satisfies a threshold value associated with the first quantity of errors correctable by the first error control code based at least in part on incrementing the counter; and

generating, at the memory system, the second error control code associated with the parameter data based at least in part on determining that the value of the counter satisfies the threshold value, wherein the second quantity of errors is greater than the first quantity of errors correctable by the first error control code.

10. The method of claim 9 , further comprising:

replacing the first error control code with the second error control code based at least in part on generating the second error control code associated with the parameter data.

11. The method of claim 9 , further comprising:

increasing the threshold value based at least in part on generating the second error control code for correcting the second quantity of errors associated with the parameter data.

12. The method of claim 1 , wherein the parameter data is stored to a first portion of the non-volatile memory device of the memory system, the method further comprising:

storing the corrected parameter data to a second portion of the non-volatile memory device of the memory system that is different than the first portion of the non-volatile memory device of the memory system.

13. A method, comprising:

receiving, at a host system, parameter data for operating a memory system based at least in part on the memory system being booted for a first occurrence;

generating, at the host system, an error control code associated with the parameter data based at least in part on receiving the parameter data from the memory system;

transmitting the error control code associated with the parameter data to the memory system based at least in part on generating the error control code associated with the parameter data;

receiving, at the host system, the parameter data and the error control code from the memory system based at least in part on the memory system being booted for a second occurrence and after transmitting the error control code associated with the parameter data to the memory system;

correcting, at the host system, a first error associated with the parameter data based at least in part on receiving the parameter data and the error control code from the memory system; and

transmitting corrected parameter data to the memory system based at least in part on correcting the first error associated with the parameter data.

14. The method of claim 13 , further comprising:

incrementing a counter based at least in part on correcting the first error associated with the parameter data, wherein a value of the counter is associated with a quantity of corrected errors of the parameter data.

15. The method of claim 14 , further comprising:

determining that the value of the counter satisfies a threshold value associated with a first quantity of errors correctable by the error control code based at least in part on incrementing the counter;

generating, at the host system, a second error control code associated with the parameter data based at least in part on determining that the value of the counter satisfies the threshold value, wherein the second error control code is configured to correct a second quantity of errors that is greater than the first quantity of errors correctable by the error control code; and

transmitting the second error control code to the memory system based at least in part on generating the second error control code.

16. The method of claim 15 , further comprising:

increasing the threshold value based at least in part on generating the second error control code for correcting the second quantity of errors associated with the parameter data.

17. The method of claim 14 , further comprising:

comparing the value of the counter to a threshold value associated with the error control code based at least in part on incrementing the counter, wherein correcting the first error associated with the parameter data is based at least in part on the value of the counter failing to satisfy the threshold value.

18. The method of claim 17 , wherein the threshold value is based at least in part on a quantity of errors that are correctable by the error control code.

19. The method of claim 14 , further comprising:

receiving, at the host system, the parameter data from the memory system based at least in part on the memory system being booted for a third occurrence;

identifying a second error associated with the parameter data based at least in part on receiving the parameter data upon the memory system being booted for the third occurrence;

incrementing the counter based at least in part on identifying the second error associated with the parameter data; and

correcting, at the host system, the second error associated with the parameter data based at least in part on identifying the second error and incrementing the counter.

20. The method of claim 19 , further comprising:

determining that the value of the counter satisfies a threshold value associated with a first quantity of errors correctable by the error control code based at least in part on incrementing the counter; and

selecting a third error control code for correcting a third quantity of errors associated with the parameter data based at least in part on determining that the value of the counter satisfies the threshold value, wherein the third error control code is configured to correct a quantity of errors that is greater than the threshold value.

21. The method of claim 20 , further comprising:

increasing the threshold value based at least in part on selecting the third error control code for correcting the third quantity of errors associated with the parameter data.

22. The method of claim 19 , further comprising:

determining that the value of the counter is above a first threshold value associated with a first quantity of errors correctable by the error control code and below a second threshold value associated with a second quantity of errors correctable by the error control code based at least in part on incrementing the counter; and

selecting a fourth error control code for correcting a fourth quantity of errors associated with the parameter data based at least in part on determining that the value of the counter is above the first threshold value and below the second threshold value, wherein the fourth error control code is configured to correct a quantity of errors that is greater than the first threshold value.

23. A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor to:

identify, upon booting a memory system for a first occurrence, parameter data for operating the memory system stored to a non-volatile memory device of the memory system;

generate, at the memory system, a first error control code associated with the parameter data based at least in part on identifying the parameter data stored to the non-volatile memory device of the memory system, the first error control code for correcting a first quantity of errors;

identify, upon booting the memory system for a second occurrence, a first error associated with the parameter data using the first error control code;

correct, at the memory system, the first error associated with the parameter data based at least in part on identifying the first error; and

generate, at the memory system, a second error control code associated with the parameter data based at least in part on correcting the parameter data, the second error control code for correcting a second quantity of errors different than the first quantity of errors.

24. The non-transitory computer-readable medium of claim 23 , wherein the instructions are further executable by the processor to:

increment a counter based at least in part on correcting the first error associated with the parameter data, wherein a value of the counter is associated with a quantity of corrected errors of the parameter data.

25. A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor to:

receive, at a host system, parameter data for operating a memory system based at least in part on the memory system being booted for a first occurrence;

generate, at the host system, an error control code associated with the parameter data based at least in part on receiving the parameter data from the memory system;

transmit the error control code associated with the parameter data to the memory system based at least in part on generating the error control code associated with the parameter data;

receive, at the host system, the parameter data and the error control code from the memory system based at least in part on the memory system being booted for a second occurrence and after transmitting the error control code associated with the parameter data to the memory system;

correct, at the host system, a first error associated with the parameter data based at least in part on receiving the parameter data and the error control code from the memory system; and

transmit corrected parameter data to the memory system based at least in part on correcting the first error associated with the parameter data.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 3, 2022
From: HUO, BINBIN
To: MICRON TECHNOLOGY, INC.
Reel/Frame 058527/0073 →
Continuity (1)
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