Semiconductor memory device
A semiconductor memory device comprises: a first pad receiving a first signal; a second pad receiving a second signal; a first memory cell array; a first sense amplifier connected to the first memory cell array; a first data register connected to the first sense amplifier and configured to store user data read from the first memory cell array; and a control circuit configured to execute an operation targeting the first memory cell array. The first memory cell array comprises a plurality of first memory strings. The first memory strings each comprise a plurality of first memory cell transistors. In a first mode of this semiconductor memory device, a command set instructing the operation is inputted via the first pad. In a second mode of this semiconductor memory device, the command set is inputted via the second pad.
1. A semiconductor memory device comprising:
a first pad configured to receive a first signal;
a second pad configured to receive a second signal;
a third pad configured to receive a third signal;
a first memory cell array comprising a plurality of first memory strings, the plurality of first memory strings each comprising a plurality of first memory cell transistors;
a first sense amplifier connected to the first memory cell array;
a first data register connected to the first sense amplifier and configured to store data read from the first memory cell array; and
a control circuit configured to execute an operation targeting the first memory cell array, wherein
the first pad is provided in plurality,
in a first mode, a command set instructing the operation is inputted via the first pads, and
in a second mode, the command set is inputted via the second pad and the third pad.
2. The semiconductor memory device according to claim 1 , wherein
the command set includes command data and address data, and
in the first mode,
when the second signal inputted to the second pad is at a first level, and
the third signal inputted to the third pad is at a second level different from the first level,
the first signal inputted to the first pads is accepted as the command data, and
when the second signal inputted to the second pad is at the second level, and
the third signal inputted to the third pad is at the first level,
the first signal inputted to the first pads is accepted as the address data.
3. The semiconductor memory device according to claim 1 , further comprising
a fourth pad configured to receive a fourth signal,
wherein in the first mode, the command set is inputted via the first pads in synchronization with the fourth signal, and
in the second mode, the command set is inputted via the second pad in synchronization with the fourth signal.
4. The semiconductor memory device according to claim 1 , further comprising:
a first receiver and a first driver connected to the first pads; and
a second receiver and a second driver connected to the second pad,
wherein in the first mode, the first receiver, the first driver, and the second receiver are driven, but the second driver is not driven, and
in the second mode, the first receiver, the first driver, the second receiver, and the second driver are driven.
5. The semiconductor memory device according to claim 1 , further comprising:
a first receiver and a first driver connected to the first pads;
a second receiver and a second driver connected to the second pad; and
a third receiver and a third driver connected to the third pad, wherein
in the first mode, the first receiver, the first driver, the second receiver, and the third receiver are driven, but the second driver and the third driver are not driven, and
in the second mode, the first receiver, the first driver, the second receiver, the second driver, the third receiver, and the third driver are driven.
6. The semiconductor memory device according to claim 1 , further comprising
a command register configured to store data inputted from the first pads and the second pad,
wherein the second pad is connected to the command register via a deserializer.
7. The semiconductor memory device according to claim 1 , further comprising
a command register configured to store data inputted from the first pads, the second pad, and the third pad,
wherein the second pad and the third pad are connected to the command register via a deserializer.
8. The semiconductor memory device according to claim 1 , wherein the semiconductor memory device
is set to the first mode after power-on, and
is set to the second mode in response to acceptance of the command set to instruct setting to the second mode.
9. The semiconductor memory device according to claim 1 , wherein
the control circuit executes:
a read operation in which the data is read from the first memory cell array and stored in the first data register; and
a data-out operation in which the data stored in the first data register is outputted from the first pads.
10. The semiconductor memory device according to claim 1 , further comprising:
a second memory cell array comprising a plurality of second memory strings, the plurality of second memory strings each comprising a plurality of second memory cell transistors;
a second sense amplifier connected to the second memory cell array; and
a second data register connected to the second sense amplifier and configured to store data read from the second memory cell array,
wherein in the second mode,
while the data stored in the first data register is being outputted from the first pads,
the command set to instruct output of the data stored in the second data register is acceptable.
11. The semiconductor memory device according to claim 1 , further comprising:
a fifth pad configured to receive a fifth signal,
wherein in the second mode,
after the command set to instruct output of the data stored in the first data register has been accepted, and
after a trigger signal is accepted,
the data is outputted from the first pads in response to a toggling of the fifth signal inputted to the fifth pad, and
after the command set to instruct output of the data stored in the first data register has been accepted, and
before the trigger signal is accepted,
the data is not outputted from the first pads, even when the fifth signal inputted to the fifth pad is toggled.
12. The semiconductor memory device according to claim 11 , further comprising
a sixth pad configured to receive a sixth signal,
wherein in the second mode, the trigger signal is generated in response to a toggling of the sixth signal inputted to the sixth pad.
13. The semiconductor memory device according to claim 1 , further comprising
a status register configured to store status data indicating an operating state of the first memory cell array,
wherein in the first mode, the status data is transmitted via the first pads, and
in a third mode, the status data is transmitted via the second pad.
14. A semiconductor memory device comprising:
a first pad configured to transmit a seventh signal;
a second pad configured to transmit an eighth signal;
a first memory cell array comprising a plurality of first memory strings, the plurality of first memory strings each comprising a plurality of first memory cell transistors;
a first sense amplifier connected to the first memory cell array;
a first data register connected to the first sense amplifier and configured to store data read from the first memory cell array;
a control circuit configured to execute an operation targeting the first memory cell array; and
a status register configured to hold status data indicating an operating state of the first memory cell array,
wherein in a first mode, the status data is transmitted via the first pad, and
in a third mode, the status data is transmitted via the second pad.
15. The semiconductor memory device according to claim 14 , further comprising
a third pad configured to transmit a ninth signal,
wherein the first pad is provided in plurality,
in the first mode, the status data is transmitted via the first pads, and
in the third mode, the status data is transmitted via the second pad and the third pad.
16. The semiconductor memory device according to claim 15 , wherein
the second pad is configured to receive a second signal,
the third pad is configured to receive a third signal, and
in the first mode,
when the second signal inputted to the second pad is at a first level, and
the third signal inputted to the third pad is at the first level,
the status data is outputted from the first pads as the seventh signal.
17. The semiconductor memory device according to claim 14 , further comprising
a fourth pad configured to receive a fourth signal,
wherein in the first mode, the status data is transmitted via the first pads in synchronization with the fourth signal, and
in the third mode, the status data is transmitted via the second pad in synchronization with the fourth signal.
18. The semiconductor memory device according to claim 14 , further comprising:
a first receiver and a first driver connected to the first pads; and
a second receiver and a second driver connected to the second pad,
wherein in the first mode, the first receiver, the first driver, and the second receiver are driven, but the second driver is not driven, and
in the third mode, the first receiver, the first driver, the second receiver, and the second driver are driven.
19. The semiconductor memory device according to claim 14 , wherein
the second pad is connected to the status register via a serializer.