Charge loss detection using a multiple sampling scheme
A memory device includes a memory array and control logic, operatively coupled with the memory array, to perform operations including causing a first current to be obtained with respect to cells of a wordline maintained at a first voltage, determining that the cells are at a second voltage lower than the first voltage, in response to determining that the cells are the second voltage, causing a voltage ramp down process to be initiated, causing a second current to be sampled with respect to the cells during the voltage ramp down process, and detecting an existence of charge loss by determining whether the second current satisfies a threshold condition in view of the first current.
1. A memory device comprising:
a memory array; and
control logic, operatively coupled with the memory array, to perform operations comprising:
causing a first current to be sampled with respect to cells of a wordline, wherein the wordline is maintained at a first voltage;
causing a second voltage ramp down process to be initiated;
causing a second current to be sampled with respect to the cells during the second voltage ramp down process; and
detecting an existence of charge loss by determining whether the second current satisfies a threshold condition with respect to the first current.
2. The memory device of claim 1 , wherein the memory array is a three-dimensional (3D) NAND device memory array, and wherein the first current and the second current are pillar currents.
3. The memory device of claim 1 , wherein the first voltage is a read pass-through voltage (V passR ).
4. The memory device of claim 1 , wherein determining whether the second current satisfies the threshold condition comprises determining whether the second current has a value that is proportional to a value of the first current based on a ratio between an index number of a particular valley of a threshold voltage (V t ) distribution, and a total number of valleys of the V t distribution.
5. The memory device of claim 1 , wherein the operations further comprise:
prior to causing the second voltage ramp down process to be initiated, causing a first voltage ramp down process to be performed to ramp down a voltage of the wordline to the first voltage.
6. The memory device of claim 1 , wherein the operations further comprise:
in response to determining that the second current satisfies the threshold condition, detecting the existence of charge loss, and causing an adjustment to a set of read voltages based on the second current to address the charge loss.
7. The memory device of claim 1 , wherein the operations further comprise:
in response to determining that the second current does not satisfy the threshold condition, continuing the second voltage ramp down process, and causing a third current to be sampled with respect to the cells during the second voltage ramp down process.
8. A method comprising:
causing a first current to be sampled with respect to cells of a wordline of a memory array, wherein the wordline is maintained at a first voltage;
causing a second voltage ramp down process to be initiated;
causing a second current to be sampled with respect to the cells during the second voltage ramp down process; and
detecting an existence of charge loss by determining whether the second current satisfies a threshold condition with respect to the first current.
9. The method of claim 8 , wherein the memory array is a three-dimensional (3D) NAND device memory array, and wherein the first current and the second current are pillar currents.
10. The method of claim 8 , wherein the first voltage is a read pass-through voltage (V passR ).
11. The method of claim 8 , wherein determining whether the second current satisfies the threshold condition comprises determining whether the second current has a value that is proportional to a value of the first current based on a ratio between an index number of a particular valley of a threshold voltage (V t ) distribution, and a total number of valleys of the V t distribution.
12. The method of claim 8 , further comprising:
prior to causing the second voltage ramp down process to be initiated, causing a first voltage ramp down process to be performed to ramp down a voltage of the wordline to the first voltage.
13. The method of claim 8 , further comprising:
in response to determining that the second current satisfies the threshold condition, detecting the existence of charge loss, and causing an adjustment to a set of read voltages based on the second current to address the charge loss.
14. The method of claim 8 , further comprising:
in response to determining that the second current does not satisfy the threshold condition, continuing the second voltage ramp down process, and causing a third current to be sampled with respect to the cells during the second voltage ramp down process.
15. A memory device comprising:
a memory array; and
control logic, operatively coupled with the memory array, to perform operations comprising:
causing a voltage of a wordline to be maintained at a second voltage corresponding to a maximum threshold voltage (V t ) for a particular valley of a V t distribution;
causing a second voltage ramp down process to be initiated;
causing a second current to be sampled with respect to cells of the wordline during the second voltage ramp down process; and
detecting an existence of charge loss by determining whether the second current has a value that is proportional to a value of a first current based on a ratio between an index number of the particular valley of the V t distribution and a total number of valleys of the V t distribution.
16. The memory device of claim 15 , wherein the memory array is a three-dimensional (3D) NAND device memory array, and wherein the first current and the second current are pillar currents.
17. The memory device of claim 15 , wherein the operations further comprise:
in response to determining that the second current has a value that is proportional to the value of the first current, detecting the existence of charge loss, and causing an adjustment to a set of read voltages based on the second current to address the charge loss.
18. The memory device of claim 15 , wherein the operations further comprise:
in response to determining that the second current does not satisfy the threshold condition, continuing the second voltage ramp down process, and causing a third current to be sampled with respect to the cells during the second voltage ramp down process.
19. The memory device of claim 15 , wherein the operations further comprise:
prior to causing the second voltage ramp down process to be initiated, causing a first voltage ramp down process to be performed to ramp down the voltage of the wordline from a first voltage to the second voltage.
20. The memory device of claim 19 , wherein the second voltage is a read pass-through voltage (V passR ).