Semiconductor structures and methods of forming the same

1. A semiconductor structure comprising:

a semiconductor substrate;

a metallization feature over the semiconductor substrate, wherein the metallization feature includes at least a first bottom corner and a second bottom corner opposite to the first bottom corner;

a first dielectric feature adjacent to the first bottom corner of the metallization feature, wherein an included angle of the first bottom corner defined by a sidewall of the first dielectric feature and a bottom surface of the metallization feature is less than 90°;

a second dielectric feature adjacent to the second bottom corner of the metallization feature, such that the metallization feature is interposed between the first dielectric feature and the second dielectric feature, and wherein the first dielectric feature and the second dielectric feature have different compositions; and

a via contact configured to connect the metallization feature to the semiconductor substrate.

2. The semiconductor structure of claim 1 , wherein an included angle of the second bottom corner defined by a sidewall of the second dielectric feature and the bottom surface of the metallization feature is greater than 90°.

3. The semiconductor structure of claim 1 , wherein an included angle of the second bottom corner defined by a sidewall of the second dielectric feature and the bottom surface of the metallization feature is less than 90°.

4. The semiconductor structure of claim 1 , wherein the first dielectric feature and the second dielectric feature have a substantially coplanar top surface with the metallization feature.

5. The semiconductor structure of claim 1 , wherein the first dielectric feature and the second dielectric feature have different compositions selected from silicon oxide, tetraethyl orthosilicate (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass BPSG, or a low-k dielectric material.

6. The semiconductor structure of claim 1 , further comprising at least a gate structure disposed over the semiconductor substrate, wherein the gate structure and the metallization feature extend lengthwise along different directions.

7. A semiconductor structure comprising:

a semiconductor substrate;

a first metallization feature over the semiconductor substrate, wherein the first metallization feature includes a first bottom corner and a second bottom corner opposite to the first bottom corner;

a second metallization feature over the semiconductor substrate, wherein the second metallization feature includes a third bottom corner and a fourth bottom corner opposite to the third bottom corner;

a first dielectric feature between the first metallization feature and the second metallization feature; and

a second dielectric feature adjacent to the first metallization feature at a side opposite to the first dielectric feature, wherein

the first metallization feature, the second metallization feature, the first dielectric feature, and the second dielectric feature are arranged along the same direction,

the first bottom corner of the first metallization feature is adjacent to the first dielectric feature and defined by an acute angle, and

the third bottom corner of the second metallization feature is adjacent to the first dielectric feature and defined by an acute angle; and wherein at least one of the second bottom corner or the fourth bottom corner is defined by an obtuse angle.

8. The semiconductor structure of claim 7 , wherein the second bottom corner is defined by the obtuse angle.

9. The semiconductor structure of claim 7 , further comprising a third dielectric feature adjacent to the second metallization feature at a side opposite to the first dielectric feature, such that the fourth bottom corner is adjacent to the third dielectric feature, wherein the fourth bottom corner is defined by the obtuse angle.

10. The semiconductor structure of claim 7 , wherein the second bottom corner is defined by the obtuse angle and the semiconductor structure further comprising a third dielectric feature adjacent to the second metallization feature at a side opposite to the first dielectric feature, such that the fourth bottom corner is adjacent to the third dielectric feature, wherein the fourth bottom corner is defined by an acute angle.

11. The semiconductor structure of claim 7 , wherein the first dielectric feature and the second dielectric feature include the same dielectric material.

12. The semiconductor structure of claim 7 , wherein the first dielectric feature and the second dielectric feature include different dielectric materials.

13. The semiconductor structure of claim 12 , further comprising a third dielectric feature adjacent to the second metallization feature at a side opposite to the first dielectric feature, such that the fourth bottom corner is adjacent to the third dielectric feature, wherein the third dielectric feature has the same composition as the second dielectric feature, and wherein the fourth bottom corner is obtuse.

14. The semiconductor structure of claim 12 , further comprising a third dielectric feature adjacent to the second metallization feature at a side opposite to the first dielectric feature, such that the fourth bottom corner is adjacent to the third dielectric feature, wherein the third dielectric feature has the same composition as the first dielectric feature, and wherein the fourth bottom corner is acute.

15. The semiconductor structure of claim 7 , further comprising a via contact configured to electrically couple the first metallization feature or the second metallization feature with the semiconductor substrate.

16. A semiconductor structure, comprising:

a semiconductor substrate, wherein a fin element extends above the semiconductor substrate, wherein the fin element extends a first direction in a top view of the semiconductor substrate;

a gate structure extending over the fin element, the gate structure extending in a second direction in the top view, the second direction perpendicular to the first direction;

a source/drain region in the fin element;

a source/drain contact extending to the source/drain region;

a dielectric layer over the source/drain contact;

a first metallization feature over the dielectric layer, wherein the first metallization feature has a first shape defined in a cross-section along first direction, the first shape comprising:

a first bottom surface,

a first sidewall extending upward from a first end of the first bottom surface at a first acute angle;

a second sidewall extending upward from a second end of the first bottom surface at a second acute angle;

a second metallization feature over the dielectric layer and coplanar with the first metallization feature, wherein the second metallization feature has a second shape defined in a cross-section along second direction, the second shape comprising:

a second bottom surface,

a third sidewall extending upward from a first end of the second bottom surface at a third acute angle;

a fourth sidewall extending upward from a second end of the second bottom surface at a first obtuse angle.

17. The semiconductor structure of claim 16 , further comprising:

a connecting via extending from the second bottom surface to the gate structure.

18. The semiconductor structure of claim 16 , wherein the first metallization feature includes a barrier layer disposed on the first bottom surface and wherein the first sidewall and the second sidewall are free of the barrier layer.

19. The semiconductor structure of claim 16 , wherein the second metallization feature includes a barrier layer disposed on the second bottom surface and extending along the fourth sidewall, wherein the third sidewall is free of the barrier layer.

20. The semiconductor structure of claim 16 , wherein the first metallization feature and the second metallization feature each have a trapezoidal shape in a cross-section in the second direction.