IP Library › Granted Patent US 11,863,071
Granted Patent B2
US 11,863,071 · App. 17/670,509 · Granted Jan 2, 2024

Power converter having smooth transition control mechanism

Inventors: Chien-Nan Chen (Hsinchu, TW); Fu-Chuan Chen (Hsinchu, TW)
Assignee: ANPEC ELECTRONICS CORPORATION
H02M3/158H02M1/0041H02M1/08
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Quick Facts
Patent No.
US 11,863,071
App. No.
17/670,509
Granted
Jan 2, 2024
Kind
B2
Abstract

A power converter having a smooth transition control mechanism is provided. An oscillator circuit outputs a clock signal. A control circuit receives the clock signal from the oscillator circuit and outputs a control signal based on the clock signal. A driver circuit outputs a high-side conduction signal and a low-side conduction signal according to the control signal. A high-side switch is turned on or off according to the high-side conduction signal from the driver circuit. A low-side switch is turned on or off according to the low-side conduction signal from the driver circuit. The oscillator circuit receives the high-side conduction signal from the driver circuit. The oscillator circuit, according to the high-side conduction signal, determines whether or not the clock signal outputted to the control circuit needs to be adjusted.

Claims (17)

1. A power converter having a smooth transition control mechanism, comprising:

an oscillator circuit configured to output a clock signal;

a control circuit connected to the oscillator circuit, and configured to receive the clock signal from the oscillator circuit and to output a control signal based on the clock signal;

a driver circuit connected to the control circuit and the oscillator circuit, and configured to output a high-side conduction signal and a low-side conduction signal;

a high-side switch, wherein a first terminal of the high-side switch is coupled to a common voltage, a control terminal of the high-side switch is connected to the driver circuit, and the high-side switch is turned on or off according to the high-side conduction signal from the driver circuit; and

a low-side switch, wherein a first terminal of the low-side switch is connected to a second terminal of the high-side switch, a second terminal of the low-side switch is grounded, a node between the first terminal of the low-side switch and the second terminal of the high-side switch is connected to a first terminal of an inductor, a second terminal of the inductor is connected to a first terminal of an output capacitor, a second terminal of the output capacitor is grounded, a control terminal of the low-side switch is connected to the driver circuit, and the low-side switch is turned on or off according to the low-side conduction signal from the driver circuit;

wherein, the oscillator circuit, according to the high-side conduction signal from the driver circuit, determines whether or not the clock signal outputted to the control circuit needs to be adjusted;

wherein, when the time point at which the high-side conduction signal transits from a high level to a low level is later than a transition time point of the clock signal, the oscillator circuit delays a pulse wave of the clock signal such that a time point at which the pulse wave of the clock signal appears is later than the time point at which the high-side conduction signal transits from the high level to the low level.

2. The power converter according to claim 1 , wherein, when a time point at which the high-side conduction signal transits from the high level to the low level is later than the transition time point of the clock signal, the oscillator circuit adjusts a frequency of the clock signal.

3. The power converter according to claim 2 , wherein, when the time point at which the high-side conduction signal transits from the high level to the low level is not later than the transition time point of the clock signal, the oscillator circuit does not adjust the clock signal.

4. The power converter according to claim 2 , wherein, when the time point at which the high-side conduction signal transits from the high level to the low level is later than the transition time point of the clock signal, the oscillator circuit reduces the frequency of the clock signal.

5. The power converter according to claim 2 , wherein the transition time point is a time point of a falling edge of the pulse wave of the clock signal.

6. The power converter according to claim 1 , wherein, the oscillator circuit includes a comparator, a first input terminal of the comparator is connected to a first terminal of an input capacitor, the first terminal of the input capacitor is connected to a current source, a second terminal of the input capacitor is grounded, a second input terminal of the comparator is coupled to a reference voltage, a third input terminal of the comparator is connected to an output terminal of the driver circuit and receives the high-side conduction signal, and an output terminal of the comparator is connected to an input terminal of the control circuit and outputs the clock signal to the control circuit.

7. The power converter according to claim 6 , wherein the oscillator circuit further includes a voltage divider circuit, an input terminal of the voltage divider circuit is coupled to an input voltage, and an output terminal of the voltage divider circuit is connected to the second input terminal of the comparator.

8. The power converter according to claim 7 , wherein the voltage divider circuit includes a first resistor and a second resistor, a first terminal of the first resistor is coupled to the input voltage, a second terminal of the first resistor is connected to a first terminal of the second resistor, a second terminal of the second resistor is grounded, and a node between the second terminal of the first resistor and the first terminal of the second resistor is connected to the second input terminal of the comparator.

9. The power converter according to claim 1 , further comprising:

an error amplifier, wherein a first input terminal of the error amplifier is connected to a node between the second terminal of the inductor and the first terminal of the output capacitor, a second input terminal of the error amplifier is coupled to a reference voltage, an output terminal of the error amplifier is connected to the control circuit, and the control circuit outputs the control signal according to an error amplified signal outputted by the error amplifier.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 14, 2022
From: CHEN, CHIEN-NAN; CHEN, FU-CHUAN
To: ANPEC ELECTRONICS CORPORATION
Reel/Frame 058996/0653 →
Priority Claims (1)
TW 110148568 · Dec 24, 2021 · national
Continuity (1)
Related Publication 20230208299A1 · Jun 29, 2023