Device isolator with reduced parasitic capacitance
Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator.
1. A method of forming an integrated circuit, comprising:
forming a first terminal over a semiconductor substrate having a first conductivity type;
forming a second terminal between the first terminal and a surface of the semiconductor substrate, the first terminal being separated from the second terminal by a dielectric layer;
forming a first p-n junction between the semiconductor substrate and the second terminal, the first p-n junction having a first orientation with respect to the substrate surface;
forming a second p-n junction between the first p-n junction and the second terminal, the second p-n junction having a second opposite orientation with respect to the substrate surface; and
forming a third p-n junction between the second p-n junction and the second terminal, the third p-n junction have the first orientation.
2. The method of claim 1 , wherein forming the first and second p-n junctions comprises forming a buried layer having a second opposite conductivity type within the substrate, the first and second p-n junctions being formed by interfaces between the buried layer and the substrate.
3. The method of claim 2 , further comprising forming a deep well of the second conductivity type that extends from the substrate surface to the buried layer.
4. The method of claim 3 , wherein the deep well laterally surrounds a surrounded portion of the semiconductor substrate having the first conductivity type, and a surface well of the second conductivity type, the third p-n junction being formed by an interface between the surrounded portion and the surface well.
5. The method of claim 4 , further comprising configuring the buried layer, the surface well, the surrounded portion and the substrate to be biased such that the first, second and third p-n junctions are reverse-biased.
6. The method of claim 1 , further comprising configuring the first, second and third p-n junctions to be reverse-biased.
7. The method of claim 1 , wherein the first terminal is configured as a bond pad.
8. The method of claim 1 , further comprising forming metallic conductors within the dielectric layer configured to provide bias voltages that reverse bias the first, second and third p-n junctions.
9. The method of claim 1 , wherein the first terminal comprises a first plate and the second terminal comprises a second plate.
10. The method of claim 1 , wherein the first terminal comprises a first coil and the second terminal comprises a second coil.
11. A method of forming an integrated circuit, comprising, comprising:
forming a metal terminal over a semiconductor substrate, the metal terminal being separated from the semiconductor substrate by a dielectric layer;
forming a first junction diode within the semiconductor substrate, the first junction diode having an anode-to-cathode direction oriented toward the metal terminal;
forming a second junction diode within the semiconductor substrate, the second junction diode having an anode-to-cathode direction oriented toward the metal terminal;
forming a third junction diode between the first and second junction diodes, the third junction diode sharing a first anode region with the first junction diode and sharing a cathode region with the second junction diode, the first anode region including a p-type region between a first n-type buried layer and an n-type well; and
forming a second anode region between the first n-type buried layer and a second n-type buried layer, the first n-type buried layer between the second n-type buried layer and the n-type well, and a fourth junction diode sharing the second anode region with the second junction diode.
12. The method of claim 11 , further comprising forming a deep n-type well that extends from the substrate surface to the second n-type buried layer, the deep n-type well connected to a first biasing terminal.
13. The method of claim 12 , wherein the deep n-type well laterally surrounds the first shared anode region.
14. The method of claim 12 , further comprising forming a first p-type contact within the first shared anode region, the first p-type contact connected to a second biasing terminal.
15. The method of claim 14 , further comprising forming a second p-type contact within the semiconductor substrate, the second p-type contact connected to a third biasing terminal and a fourth biasing terminal connected to the cathode of the first junction diode, the first, second and third and fourth biasing terminals configured to reverse-bias the first, second and third junction diodes.
16. The method of claim 11 , wherein the metal terminal is between a bondpad and the second junction diode.
17. A method of forming an integrated circuit, comprising, comprising:
forming a metal terminal over a semiconductor substrate, the metal terminal being separated from semiconductor substrate by a dielectric layer;
forming a p-type tank within the substrate, the p-type tank vertically bounded by an n-type buried layer and an n-type first well region, and laterally bounded by an n-type second well region, the p-type tank laterally extending beyond the metal terminal on all sides of the metal terminal;
forming a first junction diode between the p-type tank and the n-type first well region, the first junction diode having an anode-to-cathode direction oriented toward the metal terminal;
forming a second junction diode between the semiconductor substrate and the buried layer, the second junction diode having an anode-to-cathode direction oriented toward the metal terminal; and
forming a third junction diode between the tank and the buried layer, the third junction diode sharing an anode region with the first junction diode and sharing a cathode region with the second junction diode.
18. The method of claim 17 , wherein the n-type buried layer is a first n-type buried layer, and further comprising forming a second n-type buried layer below the first n-type buried layer and extending beyond the first n-type buried layer on all sides of the first n-type buried layer.
19. The method of claim 18 , further comprising forming a third n-type well region that surrounds the second n-type well region and conductively connects to the second n-type buried layer.
20. The method of claim 17 , wherein the metal terminal is a first metal terminal, and further comprising a second metal terminal between the first metal terminal and the first n-type well region.