Nanostructured channel regions for semiconductor devices

1. A method, comprising:

forming a superlattice structure with first and second nanostructured layers arranged in an alternating configuration on a substrate;

forming a source/drain (S/D) region on the substrate;

forming a nanostructured region through the superlattice structure;

forming a gate structure surrounding the nanostructured region about a first axis and surrounding the first nanostructured layers about a second axis different from the first axis; and

forming contact structures on the S/D region and the gate structure.

2. The method of claim 1 , wherein forming the nanostructured region comprises:

forming an opening in the superlattice structure; and

depositing a semiconductor layer in the opening.

3. The method of claim 1 , wherein forming the nanostructured region comprises:

forming an opening in the superlattice structure and the substrate; and

depositing a semiconductor layer in the opening.

4. The method of claim 1 , wherein forming the nanostructured region comprises:

forming an opening in the superlattice structure;

epitaxially growing a semiconductor layer in the opening; and

doping the semiconductor layer.

5. The method of claim 1 , wherein forming the nanostructured region comprises:

forming an opening in the superlattice structure;

epitaxially growing a semiconductor layer in the opening; and

etching the semiconductor layer to coplanarize a top surface of the semiconductor layer with a top surface of the superlattice structure.

6. The method of claim 1 , wherein forming the nanostructured region comprises:

forming a patterned masking layer with a first opening and on the superlattice structure;

etching exposed regions of the superlattice structure through the first opening to form a second opening in the superlattice structure;

depositing a semiconductor layer to fill the first and second openings; and

performing a polishing process to coplanarize a top surface of the semiconductor layer with a top surface of the patterned masking layer.

7. The method of claim 1 , wherein forming the gate structure comprises:

forming a gate opening in the superlattice structure;

depositing a high-k gate dielectric layer in the gate opening; and

depositing a negative capacitance (NC) gate dielectric layer on the high-k gate dielectric layer, wherein materials of the high-k gate dielectric layer and the NC gate dielectric layer are different from each other.

8. The method of claim 1 , wherein forming the gate structure comprises etching the second nanostructured layers from the superlattice structure.

9. The method of claim 1 , wherein forming the gate structure comprises:

depositing an oxide layer on the first nanostructured layers and on portions of the nanostructured region that are not covered by the first nanostructured layers and the substrate;

depositing a high-k gate dielectric layer on the oxide layer; and

depositing a negative capacitance (NC) gate dielectric layer on the high-k gate dielectric layer, wherein materials of the high-k gate dielectric layer and the NC gate dielectric layer are different from each other.

10. A method, comprising:

forming a stack of first and second nanostructured layers on a substrate;

forming a source/drain (S/D) region adjacent to the first and second nanostructured layers;

etching the first and second nanostructured layers to form an opening in the stack of first and second nanostructured layers;

epitaxially growing a semiconductor layer in the opening;

removing the second nanostructured layer from the stack of first and second nanostructured layers; and

forming a gate structure surrounding the semiconductor layer.

11. The method of claim 10 , further comprising doping the semiconductor layer.

12. The method of claim 10 , further comprising etching the substrate to extend the opening into the substrate through the stack of first and second nanostructured layers.

13. The method of claim 10 , further comprising:

forming a patterned masking layer with an other opening on the stack of first and second nanostructured layers prior to etching the first and second nanostructured layers; and

etching the first and second nanostructured layers through the other opening to form the opening in the stack of first and second nanostructured layers.

14. The method of claim 10 , further comprising etching the semiconductor layer to coplanarize a top surface of the semiconductor layer with a top surface of the first nanostructured layer.

15. The method of claim 10 , wherein forming the gate structure comprises:

depositing an oxide layer on the first nanostructured layer and on the semiconductor layer; and

depositing a negative capacitance gate dielectric layer on the oxide layer.

16. The method of claim 10 , further comprising:

forming a polysilicon structure on the stack of first and second nanostructured layers prior to forming the S/D region; and

removing the polysilicon structure prior to etching the first and second nanostructured layers.

17. A method, comprising:

forming first and second source/drain (S/D) regions on a substrate;

forming a stack of nanostructured horizontal channel (NHC) regions between the first and second S/D regions;

etching the stack of NHC regions to form an opening;

forming a nanostructured vertical channel (NVC) region in the opening in the stack of NHC regions; and

forming a gate structure surrounding the NHC regions and the NVC region.

18. The method of claim 17 , wherein forming the gate structure comprises:

depositing an oxide layer on the NHC regions and the NVC region; and

depositing a negative capacitance gate dielectric layer on the oxide layer.

19. The method of claim 17 , wherein forming the NVC region comprises epitaxially growing a semiconductor layer in the opening in the stack of NHC regions.

20. The method of claim 17 , wherein forming the NVC region comprises forming a doped semiconductor layer in the opening in the stack of NHC regions.