IP Library › Granted Patent US 11,869,970
Granted Patent B2
US 11,869,970 · App. 17/470,626 · Granted Jan 9, 2024

Semiconductor device including energy level in drift layer

Inventor: Kohei Oasa (Setagaya, JP)
Assignees: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation
H01L29/7827H01L27/0629H01L29/4236H01L29/66666
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Quick Facts
Patent No.
US 11,869,970
App. No.
17/470,626
Granted
Jan 9, 2024
Kind
B2
Abstract

A semiconductor device includes an upper electrode; a lower electrode; a substrate positioned between the upper electrode and the lower electrode; a buried electrode part positioned between the substrate and the upper electrode, the buried electrode part including a gate electrode; and a silicon layer positioned between the substrate and the upper electrode. The silicon layer includes a mesa part next to the buried electrode part, a first region positioned between the mesa part and the substrate, and a second region positioned between the buried electrode part and the substrate. An energy level density of the first region is greater than an energy level density of the second region.

Claims (21)

1. A semiconductor device, comprising:

an upper electrode;

a lower electrode;

a n-type substrate positioned between the upper electrode and the lower electrode;

a buried electrode part positioned between the substrate and the upper electrode, the buried electrode part including a gate electrode; and

a silicon layer positioned between the substrate and the upper electrode,

the silicon layer including

a mesa part next to the buried electrode part, and

a n-type drift layer being in direct contact with the n-type substrate, the drift layer including a first region positioned between the mesa part and the substrate, and a second region positioned between the buried electrode part and the substrate,

the first region and the second region being continuous in a direction in which the buried electrode part and the mesa part are next to each other,

an energy level density of the first region being greater than an energy level density of the second region, and a peak of an energy level density of the drift layer being located in the first region.

2. The device according to claim 1 , wherein

a crystal defect density of the first region is greater than a crystal defect density of the second region.

3. The device according to claim 1 , wherein

a hydrogen concentration of the first region is greater than a hydrogen concentration of the second region.

4. The device according to claim 1 , wherein

a plurality of the buried electrode parts and a plurality of the mesa parts extend in stripe shapes.

5. The device according to claim 1 , wherein

the buried electrode part includes a field plate electrode electrically connected with the upper electrode or the gate electrode.

6. The device according to claim 1 , wherein

the upper electrode contacts the mesa part.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 16, 2021
From: OASA, KOHEI
To: KABUSHIKI KAISHA TOSHIBA; TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
Reel/Frame 058404/0639 →
Priority Claims (1)
JP 2021-045548 · Mar 19, 2021 · national
Continuity (1)
Related Publication 20220302307A1 · Sep 22, 2022