IP Library Granted Patent US 11,870,130
Granted Patent B2
US 11,870,130 · App. 16/939,392 · Granted Jan 9, 2024

Antenna apparatus and fabrication method

Inventors: Eung San Cho (Torrance, CA); Ashutosh Baheti (Munich, DE); Saverio Trotta (Munich, DE)
Assignee: Infineon Technologies AG
H01Q1/2283H01L21/486H01L21/4853H01L21/4857H01L23/49816H01L23/66H01L2223/6677
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Quick Facts
Patent No.
US 11,870,130
App. No.
16/939,392
Granted
Jan 9, 2024
Kind
B2
Abstract

A semiconductor device includes a semiconductor die comprising a radio frequency (RF) circuit, a first dielectric layer disposed over a first surface of the semiconductor die, an antenna layer disposed over a surface of the first dielectric layer, and an antenna feeding structure coupling the antenna layer to the RF circuit of the semiconductor die, wherein the semiconductor die comprises a via, and the antenna feeding structure comprises a first portion arranged within the opening of the semiconductor die and extending to the first surface of the semiconductor die, and a second portion arranged through the first dielectric layer.

Claims (59)

1. A semiconductor device comprising:

a semiconductor die comprising a radio frequency (RF) circuit;

a first dielectric layer disposed over a first surface of the semiconductor die;

an antenna layer disposed over a surface of the first dielectric layer; and

an antenna feeding structure coupling the antenna layer to the RF circuit of the semiconductor die, wherein:

the semiconductor die comprises an opening; and

the antenna feeding structure comprises:

a first portion comprising a first via arranged within the opening of the semiconductor die and extending to the first surface of the semiconductor die,

a second portion comprising a second via arranged through the first dielectric layer and extending from the first surface of the semiconductor die to the antenna layer, and

a third portion comprising a planar conductive feature disposed on the first surface of the semiconductor die, the third portion conductively connecting the first portion to the second portion.

2. The semiconductor device of claim 1 , wherein:

the first surface of the semiconductor die is a backside of the semiconductor die.

3. The semiconductor device of claim 2 , further comprising:

a redistribution structure over a second surface of the semiconductor die, wherein the redistribution structure is electrically coupled to the RF circuit, and the second surface of the semiconductor die is a front side of the semiconductor die; and

a plurality of input/output connectors electrically coupled to the semiconductor die through the redistribution structure.

4. The semiconductor device of claim 3 , wherein:

the redistribution structure comprises a redistribution layer and a second dielectric layer, and wherein the redistribution layer is embedded in the second dielectric layer.

5. The semiconductor device of claim 1 , wherein:

the first via extends partially through the semiconductor die; and

a bottommost end of the first via is connected to a contact embedded in the semiconductor die.

6. The semiconductor device of claim 1 , wherein:

the antenna layer extends over a sidewall of the semiconductor device, and wherein a bottommost level of a portion of the antenna layer extending over the sidewall of the semiconductor device is higher than the first surface of the semiconductor die.

7. The semiconductor device of claim 1 , wherein:

the semiconductor device is an antenna-in-package (AiP) device.

8. A method of using a semiconductor device comprising: a semiconductor die comprising a radio frequency (RF) circuit; a first dielectric layer disposed over a first surface of the semiconductor die; an antenna layer disposed over a surface of the first dielectric layer; and an antenna feeding structure coupling the antenna layer to the RF circuit of the semiconductor die, wherein the semiconductor die comprises an opening, and the antenna feeding structure comprises: a first portion comprising a first via arranged within the opening of the semiconductor die and extending to the first surface of the semiconductor die, a second portion comprising a second via arranged through the first dielectric layer and extending from the first surface of the semiconductor die to the antenna layer, and a third portion comprising a planar conductive feature disposed on the first surface of the semiconductor die, the third portion conductively connecting the first portion to the second portion, the method comprising:

generating a first RF signal using the RF circuit of the semiconductor die; and

coupling the first RF signal to the antenna layer via the antenna feeding structure.

9. The method of claim 8 , further comprising transmitting the first RF signal via the antenna layer.

10. The method of claim 8 , further comprising:

receiving a second RF signal via the antenna layer; and

coupling the second RF signal to the RF circuit of the semiconductor die via the antenna feeding structure.

11. The method of claim 8 , wherein the first surface of the semiconductor die is a backside of the semiconductor die.

12. The method of claim 11 , wherein the semiconductor device further comprises:

a redistribution structure over a second surface of the semiconductor die, wherein the redistribution structure is electrically coupled to the RF circuit, and the second surface of the semiconductor die is a front side of the semiconductor die; and

a plurality of input/output connectors electrically coupled to the semiconductor die through the redistribution structure.

13. The method of claim 12 , wherein:

the redistribution structure comprises a redistribution layer and a second dielectric layer, and wherein the redistribution layer is embedded in the second dielectric layer.

14. The method of claim 8 , wherein:

the first via extends partially through the semiconductor die; and

a bottommost end of the first via is connected to a contact embedded in the semiconductor die.

15. The method of claim 8 , wherein:

the antenna layer extends over a sidewall of the semiconductor device, and wherein a bottommost level of a portion of the antenna layer extending over the sidewall of the semiconductor device is higher than the first surface of the semiconductor die.

16. The method of claim 8 , wherein the semiconductor device is an antenna-in-package (AiP) device.

17. A method of forming a semiconductor device, the method comprising:

providing a semiconductor die comprising a radio frequency (RF) circuit;

forming a first dielectric layer disposed over a first surface of the semiconductor die;

forming an antenna layer disposed over a surface of the first dielectric layer; and

forming an antenna feeding structure coupling the antenna layer to the RF circuit of the semiconductor die, wherein:

the semiconductor die comprises an opening; and

the antenna feeding structure comprises:

a first portion comprising a first via arranged within the opening of the semiconductor die and extending to the first surface of the semiconductor die,

a second portion comprising a second via arranged through the first dielectric layer and extending from the first surface of the semiconductor die to the antenna layer, and

a third portion comprising a planar conductive layer disposed on the first surface of the semiconductor die, the third portion conductively connecting the first portion to the second portion.

18. The method of claim 17 , wherein the first surface of the semiconductor die is a backside of the semiconductor die.

19. The method of claim 18 , further comprising:

forming a redistribution structure over a second surface of the semiconductor die, wherein the redistribution structure is electrically coupled to the RF circuit, and the second surface of the semiconductor die is a front side of the semiconductor die; and

forming a plurality of input/output connectors electrically coupled to the semiconductor die through the redistribution structure.

20. The method of claim 19 , wherein:

the redistribution structure comprises a redistribution layer and a second dielectric layer, and wherein the redistribution layer is embedded in the second dielectric layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2020
From: CHO, EUNG SAN; BAHETI, ASHUTOSH; TROTTA, SAVERIO
To: INFINEON TECHNOLOGIES AG
Reel/Frame 053316/0861 →
Continuity (1)
Related Publication 20220029271A1 · Jan 27, 2022
Cited By (1)
US 12,401,111