Ferroelectric memory cell

1. A memory cell of a memory array, comprising:

a substrate;

an interconnect structure bonded to the substrate via a bond interface layer, the interconnect structure coupled to a word line of the memory array;

a field effect transistor (FET) on top of the interconnect structure and electrically coupled to the interconnect structure via a gate contact;

a ferroelectric capacitor on the FET;

a source/drain contact electrically coupling the ferroelectric capacitor to a source/drain region of the FET; and

a ground contact to the ferroelectric capacitor.

2. The memory cell of claim 1 , wherein the ferroelectric capacitor comprises an electrode that includes iridium oxide.

3. The memory cell of claim 1 , wherein the source/drain region of the FET is physically coupled to the ferroelectric capacitor.

4. The memory cell of claim 1 , wherein the ferroelectric capacitor comprises one or more of lead zirconate titanate (PZT) and hafnium zirconium oxide (HfZrO 2 ).

5. The memory cell of claim 1 , wherein the ferroelectric capacitor comprises a dielectric that includes strontium ruthenium oxide (SrRuO 3 ).

6. The memory cell of claim 1 , wherein the FET comprises a gate-all-around (GAA) FET.

7. The memory cell of claim 1 , wherein the source/drain contact comprises one or more of tungsten (W), ruthenium (Ru), molybdenum (Mo), and iridium (Ir).

8. A method, comprising:

forming a transistor structure on a substrate;

bonding a carrier wafer to the transistor structure to form a bonded structure;

inverting the bonded structure;

thinning the substrate to expose the transistor structure on a back side of the bonded structure; and

coupling a ferroelectric capacitor to the transistor structure on the back side of the bonded structure to form a ferroelectric memory cell (FeRAM).

9. The method of claim 8 , further comprising:

forming an interconnect structure to electrically contact to a gate terminal of the transistor structure.

10. The method of claim 8 , further comprising:

forming a T-shaped back side source/drain contact that electrically couples a first electrode of the ferroelectric capacitor to a source/drain region of the transistor structure; and

forming metal lines that electrically couple to a second electrode of the ferroelectric capacitor.

11. The method of claim 10 , further comprising forming a through-oxide via to make contact with an other source/drain region of the transistor structure.

12. The method of claim 8 , wherein bonding the carrier wafer to the transistor structure comprises forming a bond interface layer on the carrier wafer.

13. The method of claim 12 , wherein forming the bond interface layer comprises forming an oxide in a high density plasma.

14. The method of claim 13 , wherein forming the bond interface layer further comprises planarizing the oxide.

15. The method of claim 8 , wherein forming the transistor structure comprises forming a nano-sheet gate-all-around (GAA)FET.

16. The method of claim 15 , wherein forming the GAAFET comprises forming epitaxial source/drain regions.

17. A ferroelectric memory cell (FeRAM), comprising:

a pair of transistors on a front side of a substrate and sharing a source/drain region;

an interconnect structure coupled to respective gate terminals of the transistors;

a ferroelectric capacitor formed on a back side of the substrate and electrically coupled to the shared source/drain region via a source/drain contact;

a through-oxide via (TOV) coupled to one of the pair of transistors; and

a ground contact electrically coupled to the ferroelectric capacitor.

18. The FeRAM of claim 17 , further comprising a carrier wafer bonded to the interconnect structure to form a bonded structure.

19. The FeRAM of claim 18 , wherein the bonded structure includes a bond interface layer made of a silicon oxide material.

20. The FeRAM of claim 17 , wherein the pair of transistors comprise one or more of FinFETs, planar FETs, and GAAFETs.