Display device having a lower pattern overlapping an active pattern

1. A display device comprising:

a substrate;

a first conductive layer including a lower pattern disposed on the substrate;

a first transistor disposed on the substrate and including a first active pattern and a first gate electrode;

a second transistor disposed on the substrate and including a second active pattern and a second gate electrode;

a third transistor disposed on the substrate and including a third active pattern and a third gate electrode; and

a capacitor including a first terminal connected to the first gate electrode, and a second terminal connected to the third transistor, wherein

the lower pattern has a planar area that is greater than a planar area of the first active pattern and overlaps an entirety of the first active pattern, and

the lower pattern includes a portion that does not overlap the first active pattern in a plan view.

2. The display device of claim 1 , wherein

the third active pattern is spaced apart from the first active pattern, and

the third active pattern does overlap the lower pattern.

3. The display device of claim 2 , further comprising:

a second conductive layer including the first gate electrode; and

a third conductive layer disposed in a different layer from the first conductive layer and the second conductive layer,

wherein the first active pattern includes a first channel region, a first source region and a first drain region,

the third active pattern includes a third channel region, a third source region and a third drain region, and

the first drain region and the third source region are electrically connected to each other through the third conductive layer.

4. The display device of claim 3 , further comprising:

a first insulating layer disposed on the second conductive layer,

wherein the third conductive layer includes a capacitor electrode as the second terminal, the capacitor electrode being disposed on the first insulating layer, and

the capacitor electrode is electrically connected to the first drain region and the third source region.

5. The display device of claim 4 , wherein

the capacitor electrode overlaps the first gate electrode to form the capacitor.

6. The display device of claim 5 , wherein

the capacitor electrode is electrically connected to the lower pattern.

7. The display device of claim 6 , further comprising:

a second insulating layer disposed on the third conductive layer;

a pixel electrode layer including a pixel electrode disposed on the second insulating layer; and

an emission layer disposed on the pixel electrode,

wherein the pixel electrode is electrically connected to the capacitor electrode.

8. The display device of claim 7 , wherein

the second active pattern is spaced apart from the first and third active patterns,

the third conductive layer further includes a driving voltage line and a data line,

the first source region of the first active pattern is electrically connected to the driving voltage line, and

the second active pattern includes a second source region electrically connected to the data line.

9. The display device of claim 7 , further comprising:

a fourth conductive layer disposed between the second insulating layer and the pixel electrode layer, and

the fourth conductive layer further includes a driving voltage line and a data line.

10. The display device of claim 7 , wherein

the third conductive layer further includes a driving voltage line and a data line.

11. The display device of claim 1 , wherein

the third active pattern is connected to the first active pattern.