Fault tolerant computation method and apparatus for quantum Clifford circuit, device, and chip
View Patent ↗This application discloses a fault tolerant computation method and device for a quantum Clifford circuit with reduced resource requirement. The method includes decomposing a quantum Clifford circuit into s logic Clifford circuits and preparing auxiliary quantum states corresponding to the s logic Clifford circuits. For each logic Clifford circuit, the method further includes teleporting an input quantum state corresponding to the logic Clifford circuit to an auxiliary qubit, processing a quantum state obtained after the teleportation by the logic Clifford circuit to obtain a corresponding output quantum state; measuring a corresponding error symptom based on the input quantum state and the auxiliary quantum state; and performing error correction on the output quantum state according to the error symptom to obtain an error-corrected output quantum state.
1. A fault tolerant quantum computation device, comprising a quantum Clifford circuit decomposed into s logic Clifford circuits, s being a positive integer, wherein:
the s logic Clifford circuits of the quantum Clifford circuit are configured to process k logic qubits;
an average number of physical qubits associated with the s logic Clifford circuits is at or less than 0(k);
an average number of quantum gates associated with the s logic Clifford circuits is at or less than 0(k 2 /log(k)); and
an average number of auxiliary quantum states prepared associated with the s logic Clifford circuits is at or less than 0(1).
2. The fault tolerant quantum computation device of claim 1 , wherein an average real-time circuitry depth associated with the s logic Clifford circuits is at or less than 0(1).
3. The fault tolerant quantum computation device of claim 1 , further comprising a classical processor configured to perform a circuit decomposition of the quantum Clifford circuit into the s logic Clifford circuits.
4. The fault tolerant quantum computation device of claim 3 , wherein the classical processor is configured to:
transform the quantum Clifford circuit into a form of a symplectic matrix to obtain a symplectic matrix representation of the quantum Clifford circuit; and
decompose the symplectic matrix representation of the quantum Clifford circuit to obtain symplectic matrix representations of the s logic Clifford circuits.
5. The fault tolerant quantum computation device of claim 1 , wherein each of the s logic Clifford circuits is associated with an auxiliary quantum state preparation circuit for preparing an auxiliary quantum state.
6. The fault tolerant quantum computation device of claim 5 , further comprising a measurement component configured to measure an error symptom of each of the s logic Clifford circuits based on an input quantum state and the auxiliary quantum state corresponding each of the s logic Clifford circuits.
7. The fault tolerant quantum computation device of claim 6 , wherein the measurement component is configured to:
process the input quantum state and the auxiliary quantum state each of the s logic Clifford circuits using a controlled NOT (CNOT) gate;
measure a physical qubit corresponding to the input quantum state in Pauli-Z direction, and measure a physical qubit corresponding to the auxiliary quantum state in Pauli-X direction, to obtain a measurement result; and
determine the error symptom corresponding to each of the s logic Clifford circuits based on the measurement result.
8. The fault tolerant quantum computation device of claim 7 , further comprising an error correction component for performing correction on an output quantum state of each of the s logic Clifford circuits according to the error symptom to obtain an error-corrected output quantum state.
9. The fault tolerant quantum computation device of claim 8 , wherein the error correction component is configured to:
determine, based on the measurement result, a logic Pauli-X operator and a logic Pauli-Z operator that need to be error-corrected;
determine an occurrence position and a type of an error based on the error symptom corresponding to each of the s logic Clifford circuits and by using a decoding algorithm corresponding to a quantum error correction (QEC) code; and
perform an error correction on the output quantum state corresponding to each of the s logic Clifford circuits to obtain the error-corrected output quantum state after the logic Pauli-X operator and the logic Pauli-Z operator that need to be error corrected are corrected.
10. The fault tolerant quantum computation device of claim 8 , wherein the auxiliary quantum state preparation circuit is configured to:
determine the auxiliary quantum state corresponding to each of the s logic Clifford circuits;
build fault tolerant preparation circuits corresponding to the auxiliary quantum state; and
prepare the auxiliary quantum state by using the fault tolerant preparation circuits in parallel in a pipelined manner.
11. The fault tolerant quantum computation device of claim 5 , wherein s is not greater than 9.
12. The fault tolerant quantum computation device of claim 5 , wherein each of the s logic Clifford circuits comprises a single-type gate, and the single-type gate comprises a controlled NOT (CNOT) gate, a Hadamard gate, or a phase gate.
13. The fault tolerant quantum computation device of claim 12 , wherein the auxiliary quantum state comprises at least one of the following: an auxiliary quantum state corresponding to the CNOT gate, an auxiliary quantum state corresponding to the Hadamard gate, and an auxiliary quantum state corresponding to the phase gate.
14. The fault tolerant quantum computation device of claim 1 , further comprising a quantum teleportation component configured for teleporting an input quantum state to an auxiliary qubit corresponding to one of the s logic Clifford circuits.
15. The fault tolerant quantum computation device of claim 1 , comprising a superconducting quantum computation (QC) chip for implementing the quantum Clifford circuit.
16. The fault tolerant quantum computation device of claim 15 , wherein:
the superconducting QC chip comprises m layer of physical qubits having a three-dimensional integrated packaging, m being an integer greater than 1; and
each layer of physical qubits being used for forming a quantum state, the quantum state comprising an input quantum state, an auxiliary quantum state, or an output quantum state associated with the s logic Clifford circuits.
17. The fault tolerant quantum computation device of claim 16 , wherein the physical qubits in each layer are located in a same code block.
18. The fault tolerant quantum computation device of claim 16 , wherein coupling between physical qubits in a same layer is achieve via resonant cavity coupling.
19. The fault tolerant quantum computation device of claim 16 , wherein physical qubits at a same position in different layers are coupled by a data bus.
20. The fault tolerant quantum computation device of claim 19 , wherein the data bus connects the physical qubits at the same position in the different layers using deep through-silicon vias in the different layers.