Semiconductor memory device

1. A semiconductor memory device comprising:

a first memory cell;

a second memory cell;

a first word line coupled to the first memory cell;

a second word line coupled to the second memory cell;

a semiconductor layer interposed between the first memory cell and the second memory cell; and

a first bit line capable of being electrically coupled to both the first memory cell and the second memory cell,

wherein the semiconductor memory device is configured to execute a first operation, a second operation, and a third operation, wherein

in the first operation, a first voltage is applied to a word line corresponding to a non-selected memory cell,

in the second operation, after the first operation, a second voltage higher than the first voltage is applied to the word line corresponding to the non-selected memory cell,

in the third operation, after the second operation, a third voltage higher than the second voltage is applied to the word line corresponding to the non-selected memory cell, and a fourth voltage lower than both the third voltage and the second voltage is applied to a word line corresponding to a selected memory cell,

the semiconductor memory device is further configured to:

execute the first operation, the second operation, and the third operation when receiving a write command for the first memory cell; and

execute the third operation when receiving a write command for the second memory cell,

wherein

data writing into the second memory cell is executed after data writing into the first memory cell is executed.

2. The semiconductor memory device according to claim 1 , wherein the write command for the second memory cell is received after the write command for the first memory cell is received.

3. The semiconductor memory device according to claim 1 , wherein

when receiving the write command for the second memory, the semiconductor memory device is configured to execute the third operation without executing the first and second operations during a period between the semiconductor memory device entering to a busy state and returning to a ready state.

4. The semiconductor memory device according to claim 1 , wherein, the first voltage is applied to the second word line when data is read from the first memory cell, and

the fourth voltage turns on a memory cell.

5. The semiconductor memory device according to claim 4 , wherein, the first voltage is a negative voltage.

6. The semiconductor memory device according to claim 1 , further comprising:

a third memory cell; and

a third word line coupled to the third memory cell,

wherein the second word line is positioned between the first word line and the third word line, and

the semiconductor memory device is further configured to write data into the second memory cell after data is written into the first memory cell and the third memory cell.

7. The semiconductor memory device according to claim 1 , wherein the first operation is executed to verify the non-selected memory cell,

the second operation includes a first program operation to increase a threshold value of the non-selected memory cell based on a result of the first operation, and

the third operation includes a second program operation to write data received from a controller, into the selected memory cell.

8. The semiconductor memory device according to claim 7 , wherein the second program operation includes:

a first write operation using a first program verify voltage; and

a second write operation after the first write operation and using a second program verify voltage higher than the first program verify voltage,

wherein, when the first write operation in the third operation is executed, the first operation and the second operation is executed, and

when the second write operation in the third operation is executed, the first operation and the second operation is not executed.

9. The semiconductor memory device according to claim 7 , wherein the second operation includes an operation of programming a memory cell which is determined in the first operation that a threshold value is lower than or equal to the first voltage.

10. A method of controlling a semiconductor memory device including a first memory cell, a second memory cell, a first word line, a second word line, a semiconductor layer and a first bit line, the first word line being coupled to the first memory cell, the second word line being coupled to the second memory cell, the semiconductor layer being interposed between the first memory cell and the second memory cell, the first bit line being capable of being electrically coupled to both the first memory cell and the second memory cell, the method comprising:

executing, in response to a write command for the first memory cell, a first operation, a second operation after executing the first operation, and a third operation after executing the second operation, the first operation including applying a first voltage to a word line corresponding to a non-selected memory cell, the second operation including applying a second voltage higher than the first voltage to the word line corresponding to the non-selected memory cell, and the third operation including applying a third voltage higher than the second voltage to the word line corresponding to the non-selected memory cell and applying a fourth voltage lower than both the third voltage and the second voltage to a word line corresponding to a selected memory cell; and

executing, in response to a write command for the second memory cell, the third operation,

wherein

data writing into the second memory cell is executed after data writing into the first memory cell is executed.

11. The method of controlling the semiconductor memory device according to claim 10 , wherein the write command for the second memory cell is received after the write command for the first memory cell is received.

12. The method of controlling the semiconductor memory device according to claim 10 , wherein, in response to the write command for the second memory, the third operation is executed without executing the first and second operations during a period between the semiconductor memory device entering to a busy state and returning to a ready state.

13. The method of controlling the semiconductor memory device according to claim 10 , wherein, the first voltage is applied to the second word line when data is read from the first memory cell, and

the fourth voltage turns on a memory cell.

14. The method of controlling the semiconductor memory device according to claim 13 , wherein, the first voltage is a negative voltage.

15. The method of controlling the semiconductor memory device according to claim 10 , wherein

the semiconductor memory device further includes: a third memory cell; and

a third word line coupled to the third memory cell,

wherein the second word line is positioned between the first word line and the third word line, and

wherein data is written into the second memory cell after data is written into the first memory cell and the third memory cell.

16. The method of controlling the semiconductor memory device according to claim 10 , wherein the first operation is executed to verify the non-selected memory cell,

the second operation includes a first program operation to increase a threshold value of the non-selected memory cell based on a result of the first operation, and

the third operation includes a second program operation to write data received from a controller, into the selected memory cell.

17. The method of controlling the semiconductor memory device according to claim 16 , wherein the second program operation includes:

a first write operation using a first program verify voltage; and

a second write operation after the first write operation and using a second program verify voltage higher than the first program verify voltage,

wherein, when the first write operation in the third operation is executed, the first operation and the second operation is executed, and

when the second write operation in the third operation is executed, the first operation and the second operation is not executed.

18. The method of controlling the semiconductor memory device according to claim 16 , wherein the second operation includes an operation of programming a memory cell which is determined in the first operation that a threshold value is lower than or equal to the first voltage.