IP Library › Granted Patent US 11,876,077
Granted Patent B2
US 11,876,077 · App. 17/199,458 · Granted Jan 16, 2024

Semiconductor device and method of manufacturing the same

Inventors: Yi-Jen Lo (New Taipei, TW); Hsih Yang Chiu (Taoyuan, TW); Ching Hung Chang (Taoyuan, TW); Chiang-Lin Shih (New Taipei, TW)
Assignee: NANYA TECHNOLOGY CORPORATION
H01L25/0657H01L24/08H01L24/89H01L25/50H01L2224/08146H01L2224/80895H01L2225/06541
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Quick Facts
Patent No.
US 11,876,077
App. No.
17/199,458
Granted
Jan 16, 2024
Kind
B2
Abstract

The disclosure provides a method of manufacturing a semiconductor device including bonding a second device wafer to a first device wafer, such that a first bonding interface including a fusion-bonding interface is formed between the first device wafer and the second device wafer, wherein the first device wafer and the second device wafer are the same kind of device wafer. A semiconductor device is also provided.

Claims (16)

1. A method of manufacturing a semiconductor device, comprising:

bonding a second device wafer to a first device wafer, such that a first bonding interface including a fusion-bonding interface is formed between the first device wafer and the second device wafer, wherein the first device wafer and the second device wafer are the same kind of device wafer,

wherein the first device wafer comprises a first dielectric layer and a first conductive portion, the second device wafer comprises a second dielectric layer and a second conductive portion, and the fusion bonding interface is formed by entire surfaces between the first dielectric layer and the second dielectric layer only;

forming an opening, wherein the opening penetrates through the first bonding interface to expose a portion of the second device wafer and a portion of the first device wafer, wherein the first conductive portion and the second conductive portion are exposed by the opening.

2. The method as claimed in claim 1 , wherein the first dielectric layer directly contacts the second dielectric layer.

3. The method as claimed in claim 1 , further comprising:

filling a conductive metal in the opening to form a vertical connector, and the second device wafer are electrically coupled to the first device wafer through the vertical connector.

4. The method as claimed in claim 1 , wherein forming the opening includes:

performing a punching process to expose a top surface of the first conductive portion and a top surface of the second conductive portion.

5. The method as claimed in claim 1 , further comprising:

bonding a third device wafer to the second device wafer, such that a second bonding interface including a fusion-bonding interface is formed between the second device wafer and the third device wafer, wherein the second device wafer and the third device wafer are the same kind of device wafer.

6. The method as claimed in claim 5 , wherein the first device wafer, the second device wafer, and the third device wafer are memory device wafer.

7. The method as claimed in claim 5 , wherein the third device wafer comprises a third dielectric layer, and the second dielectric layer directly contacts the third dielectric layer.

8. The method as claimed in claim 1 , further comprising:

bonding the first device wafer to a dummy wafer, such that a third bonding interface including a fusion-bonding interface is formed between the dummy wafer and the first device wafer before the first bonding interface is formed.

9. The method as claimed in claim 8 , wherein the dummy wafer comprises a dielectric material layer, and the dielectric material layer directly contacts the first dielectric layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 12, 2021
From: LO, YI-JEN; CHIU, HSIH YANG; CHANG, CHING HUNG; SHIH, CHIANG-LIN
To: NANYA TECHNOLOGY CORPORATION
Reel/Frame 055569/0855 →
Continuity (1)
Related Publication 20220293561A1 · Sep 15, 2022
Cited By (1)
US 12,463,043