Epitaxial source/drain structures for multigate devices and methods of fabricating thereof
Epitaxial source/drain structures for enhancing performance of multigate devices, such as fin-like field-effect transistors (FETs) or gate-all-around (GAA) FETs, and methods of fabricating the epitaxial source/drain structures, are disclosed herein. An exemplary device includes a dielectric substrate. The device further includes a channel layer, a gate disposed over the channel layer, and an epitaxial source/drain structure disposed adjacent to the channel layer. The channel layer, the gate, and the epitaxial source/drain structure are disposed over the dielectric substrate. The epitaxial source/drain structure includes an inner portion having a first dopant concentration and an outer portion having a second dopant concentration that is less than the first dopant concentration. The inner portion physically contacts the dielectric substrate, and the outer portion is disposed between the inner portion and the channel layer. In some embodiments, the outer portion physically contacts the dielectric substrate.
1. A semiconductor structure comprising:
a dielectric substrate; and
a channel layer, a gate disposed over the channel layer, and an epitaxial source/drain structure disposed adjacent to the channel layer, wherein the channel layer, the gate, and the epitaxial source/drain structure are disposed over the dielectric substrate, and further wherein the epitaxial source/drain structure includes:
an inner portion having a first dopant concentration, wherein the inner portion physically contacts the dielectric substrate, and
an outer portion having a second dopant concentration, wherein the second dopant concentration is less than the first dopant concentration and the outer portion is disposed between the inner portion and the channel layer.
2. The semiconductor structure of claim 1 , wherein the gate wraps the channel layer and the channel layer physically contacts the dielectric substrate.
3. The semiconductor structure of claim 1 , wherein the gate surrounds the channel layer and the gate physically contacts the dielectric substrate.
4. The semiconductor structure of claim 1 , wherein the outer portion physically contacts the dielectric substrate.
5. The semiconductor structure of claim 1 , wherein the inner portion includes a lower portion having a first composition that physically contacts the dielectric substrate and an upper portion having a second composition disposed over the lower portion, wherein the second composition is different than the first composition.
6. The semiconductor structure of claim 5 , wherein the first composition includes a first germanium concentration and the second composition includes a second germanium concentration that is greater than the first germanium concentration.
7. The semiconductor structure of claim 1 , wherein the epitaxial source/drain structure further includes a capping layer disposed over the inner portion and the outer portion.
8. The semiconductor structure of claim 1 , wherein the dielectric substrate is disposed between a first isolation feature and a second isolation feature.
9. A semiconductor structure comprising:
a dielectric substrate; and
a transistor having a channel layer, a gate disposed over at least two sides of the channel layer, and an epitaxial source/drain structure disposed adjacent to the channel layer, wherein the channel layer, the gate, and the epitaxial source/drain structure are disposed over the dielectric substrate, and further wherein the epitaxial source/drain structure includes:
a first epitaxial sidewall and a second epitaxial sidewall, wherein the first epitaxial sidewall and the second epitaxial sidewall each have a first dopant concentration, and
an epitaxial layer disposed between the first epitaxial sidewall and the second epitaxial sidewall, wherein the epitaxial layer physically contacts the dielectric substrate and the epitaxial layer has a second dopant concentration that is greater than the first dopant concentration.
10. The semiconductor structure of claim 9 , wherein the channel layer is a fin that physically contacts the dielectric substrate and the gate wraps the fin.
11. The semiconductor structure of claim 9 , wherein the channel layer is a suspended semiconductor layer, the gate surrounds the suspended semiconductor layer, and the gate physically contacts the dielectric substrate.
12. The semiconductor structure of claim 9 , wherein:
the channel layer is a first channel layer and the semiconductor structure further includes a second channel layer disposed over the first channel layer; and
the first epitaxial sidewall is disposed between the first channel layer and the epitaxial layer and between the second channel layer and the epitaxial layer; and
the first epitaxial sidewall extends continuously from the first channel layer to the second channel layer and physically contacts the dielectric substrate.
13. The semiconductor structure of claim 9 , wherein:
the channel layer is a first channel layer and the semiconductor structure further includes a second channel layer disposed over the first channel layer;
the first epitaxial sidewall is disposed between the first channel layer and the epitaxial layer and between the second channel layer and the epitaxial layer; and
the first epitaxial sidewall is interrupted by the epitaxial layer, wherein the epitaxial layer is disposed between and separates the first epitaxial sidewall and the dielectric substrate.
14. The semiconductor structure of claim 13 , wherein the epitaxial layer is further disposed between and separates a first portion of the first epitaxial sidewall disposed along a first sidewall of the first channel layer and a second portion of the first epitaxial sidewall disposed along a second sidewall of the second channel layer.
15. The semiconductor structure of claim 9 , wherein the dielectric substrate includes a first dielectric layer that wraps a second dielectric layer.
16. A method comprising:
forming a source/drain recess that extends a depth into a semiconductor substrate;
epitaxially growing a first semiconductor layer having a first dopant concentration in the source/drain recess, wherein the first semiconductor layer is disposed along sidewalls and a bottom of the source/drain recess, wherein a thickness of the first semiconductor layer along the bottom of the source/drain recess is less than the depth;
epitaxially growing a second semiconductor layer in the source/drain recess and over the first semiconductor layer, wherein the second semiconductor layer has a second dopant concentration greater than the first dopant concentration; and
replacing the semiconductor substrate with a dielectric substrate, wherein the second semiconductor layer physically contacts the dielectric substrate.
17. The method of claim 16 , wherein the replacing the semiconductor substrate with the dielectric substrate includes:
bonding a carrier wafer to a back-end-of-line structure disposed over a frontside of the semiconductor substrate;
performing an etching process to remove the semiconductor substrate and a portion of the first semiconductor layer disposed below a top surface of the semiconductor substrate, wherein the etching process exposes the second semiconductor layer; and
forming a dielectric layer over the exposed second semiconductor layer.
18. The method of claim 17 , wherein the carrier wafer is a first carrier wafer, the method further comprising:
bonding the dielectric substrate to a second carrier wafer; and
removing the first carrier wafer from the back-end-of-line structure.
19. The method of claim 17 , wherein the performing the etching process further removes a portion of the second semiconductor layer disposed below the top surface of the semiconductor substrate.
20. The method of claim 16 , wherein no well implant process is performed on the semiconductor substrate.