Non-fighting level shifters

1. A level shifter circuit, comprising:

a first current mirror coupled between a power terminal and a ground terminal, wherein the first current mirror comprises a first n-type transistor gated by an input signal, and wherein the first current mirror is self-timed;

a second current mirror coupled between the power terminal and the ground terminal, wherein the second current mirror comprises a second n-type transistor gated by an inverse of the input signal, and wherein the second current mirror is self-timed;

a level shifter, wherein the level shifter includes a first transistor coupled to the first current mirror and a second transistor coupled to the second current mirror, wherein the first current mirror and the second current mirror control a state of the first transistor and the second transistor;

a first shoot-thru current section comprising a first inverter and a second inverter directly coupled between a gate of the first transistor and the first current mirror; and

a second shoot-thru current section comprising a third inverter and a fourth inverter directly coupled between a gate of the second transistor and the second current mirror.

2. The level shifter circuit of claim 1 , wherein the first current mirror controls a voltage at a gate of the second transistor; and

wherein the second current mirror controls the voltage at the gate of the first transistor.

3. The level shifter circuit of claim 1 , wherein the first current mirror comprises:

a third transistor coupled between the power terminal and a fourth transistor,

the fourth transistor coupled between the third transistor and the ground terminal, and

a fifth transistor coupled between the power terminal and a drain terminal of the first transistor;

wherein the second current mirror comprises:

a sixth transistor coupled between the power terminal and a seventh transistor,

the seventh transistor coupled between the sixth transistor and the ground terminal, and

an eighth transistor coupled between the power terminal and a drain terminal of the second transistor; and wherein

a gate terminal of the third transistor is coupled to a drain terminal of the third transistor and to a gate terminal of the fifth transistor and a gate terminal of the sixth transistor is coupled to a drain terminal of the sixth transistor and to a gate terminal of the eighth transistor.

4. The level shifter circuit of claim 3 , wherein the first current mirror further comprises a ninth transistor coupled between the fourth transistor and the first n-type transistor; and the second current mirror further comprises a tenth transistor coupled between the seventh transistor and the second n-type transistor.

5. The level shifter circuit of claim 3 , wherein the third transistor, the fifth transistor, the sixth transistor, and the eighth transistor are p-type transistors, and the fourth transistor and the seventh transistor are n-type transistors.

6. The level shifter circuit of claim 1 , wherein the first shoot-thru current section and the second shoot-thru current section are configured to control a timing of the first current mirror and the second current mirror in the level shifter circuit.

7. The level shifter circuit of claim 1 , wherein

each of the inverters is configured to introduce a delay in the level shifter circuit.

8. The level shifter circuit of claim 1 , wherein the level shifter further comprises:

a third transistor coupled between the first transistor and ground and a fourth transistor coupled between the second transistor and ground, wherein the fourth transistor is gated by an input signal.

9. The level shifter circuit of claim 8 , wherein the level shifter further comprises:

a fifth transistor coupled between the first transistor and the third transistor and a sixth transistor coupled between the second transistor and the fourth transistor, wherein the first current mirror is coupled to a drain terminal of the first transistor and the second current mirror is coupled to a drain terminal of the second transistor; and

wherein the first current mirror is configured to control a voltage at a gate terminal of the second transistor via the fifth transistor and the second current mirror is configured to control a voltage at a gate terminal of the first transistor via the sixth transistor.

10. The level shifter circuit of claim 1 , wherein one or more transistors of the level shifter, the first current mirror, and the second current mirror are low voltage transistors and the level shifter circuit further comprising:

at least one transistor coupled to a drain of a low voltage transistor and configured to control a voltage at the drain of the low voltage transistor.

11. The level shifter circuit of claim 1 , wherein an input terminal of the level shifter is coupled to an input/output circuit.

12. A level shifter circuit, comprising:

a first current mirror coupled between a power terminal and a ground terminal, wherein the first current mirror comprises a first n-type transistor gated by an input signal, and wherein the first current mirror is self-timed;

a second current mirror coupled between the power terminal and the ground terminal, wherein the second current mirror comprises a second n-type transistor gated by an inverse of the input signal, and wherein the second current mirror is self-timed;

a level shifter including a first p-type transistor and a second p-type transistor, wherein the first current mirror and the second current mirror are configured to control a voltage at a gate of the first p-type transistor and the second p-type transistor;

a first shoot-thru current section comprising a first inverter and a second inverter directly coupled between a gate of the first p-type transistor and the first current mirror; and

a second shoot-thru current section comprising a third inverter and a fourth inverter directly coupled between a gate of the second p-type transistor and the second current mirror.

13. The level shifter circuit of claim 12 , wherein the first current mirror or the second current mirror further comprise:

a third p-type transistor coupled between the power terminal and the first n-type transistor;

a fourth p-type transistor coupled between the power terminal and a drain of the first p-type transistor, wherein a gate of the fourth p-type transistor is coupled to the gate of the third p-type transistor;

a fifth p-type transistor coupled between the power terminal and the second-n-type transistor; and

a sixth p-type transistor coupled between the power terminal and a drain of the second p-type transistor, wherein the gate of the sixth p-type transistor is coupled to the gate of the fifth p-type transistor.

14. The level shifter circuit of claim 13 , wherein the level shifter further comprises:

a third n-type transistor coupled between the first p-type transistor and ground; and

a fourth n-type transistor coupled between the second p-type transistor and ground.

15. The level shifter circuit of claim 12 ,

wherein each of the inverters is configured to introduce a delay in the level shifter circuit.

16. The level shifter circuit of claim 12 , wherein the level shifter further comprises:

a third n-type transistor coupled between the first p-type transistor and ground, and a fourth n-type transistor coupled between the second p-type transistor and ground, wherein the fourth n-type transistor is gated by the input signal, wherein the gate of the first p-type transistor is coupled to a drain of the fourth n-type transistor, and wherein the gate of the second p-type transistor is coupled to the drain of the third n-type transistor.

17. The level shifter circuit of claim 12 , wherein one or more transistors of the level shifter and the first current mirror are low voltage transistors and the level shifter circuit further comprising:

at least one high voltage transistor coupled to a drain of a low voltage transistor and configured to control a voltage at the drain of the low voltage transistor.

18. An input/output (I/O) circuit comprising:

a level shifter comprising:

a first current mirror coupled between a power terminal and a ground terminal, wherein the first current mirror comprises a first n-type transistor gated by an input signal, and wherein the first current mirror is self-timed;

a second current mirror coupled between the power terminal and the ground terminal, wherein the second current mirror comprises a second n-type transistor gated by an inverse of the input signal, and wherein the second current mirror is self-timed;

a level shifter section, wherein the level shifter section includes a first transistor coupled to the first current mirror and a second transistor coupled to the second current mirror, and a high voltage transistor coupled to a drain of the first transistor and a second high voltage transistor coupled to the drain of the second transistor;

a first shoot-thru current section comprising a first inverter and a second inverter directly coupled between a gate of the first transistor and the first current mirror; and

a second shoot-thru current section comprising a third inverter and a fourth inverter directly coupled between a gate of the second transistor and the second current mirror.

19. The I/O circuit of claim 18 , wherein the first n-type transistor and the second n-type transistor are low voltage transistors.

20. The I/O circuit of claim 18 , wherein the first current mirror controls a voltage at a gate of the second transistor; and

wherein the second current mirror controls the voltage at the gate of the first transistor.