High-speed hardware-based traffic analyzer integration with speed test control application
In some examples, high-speed hardware-based traffic analyzer integration with speed test control application may include receiving, from a speed test control application, speed test control instructions and data connection instructions to perform an upload and download high-speed test associated with network traffic for a network. The speed test control instructions and the data connection instructions may be forwarded to a speed test control server. A hardware-based traffic analyzer may perform, based on the speed test control instructions and the data connection instructions, the high-speed test associated with the network traffic for the network.
1. An apparatus comprising:
at least one hardware processor;
a memory storing machine readable instructions, the machine readable instructions, when executed by at least one hardware processor, cause the at least one hardware processor to:
receive, from a speed test control application installed on the apparatus, speed test control instructions and data connection instructions for the apparatus to perform a high-speed test associated with network traffic of a network; and
forward the speed test control instructions and the data connection instructions to a speed test control server; and
a hardware-based traffic analyzer comprising a data port to, based on the speed test control instructions and the data connection instructions forwarded to the speed test control server, establish a connection with the speed test control server, and perform the high-speed test associated with the network traffic of the network by transmitting and receiving relatively high bit-rate data to and from the speed test control server, and a control port to transmit relatively slow-speed control traffic to the speed test control application,
wherein the at least one hardware processor is further to:
receive results of the high-speed test from the speed test control server; and
transmit the results of the high-speed test to the speed test control application.
2. The apparatus according to claim 1 , wherein the speed test control server is located in a Cloud environment.
3. The apparatus according to claim 1 , wherein the speed test control application is implemented by a central processing unit (CPU) of the apparatus.
4. The apparatus according to claim 1 , wherein the hardware-based traffic analyzer is implemented to include a Field Programmable Gate Array (FPGA) to handle the relatively high bit-rate data.
5. The apparatus according to claim 1 , wherein the machine readable instructions, when executed by the at least one hardware processor, further cause the at least one hardware processor to:
utilize Transmission Control Protocol/Internet Protocol (TCP/IP) to transmit and receive the relatively high bit-rate data between the speed test control server and the hardware-based traffic analyzer.
6. A method for comprising:
receiving, by at least one hardware processor in an apparatus, from a speed test control application installed on the apparatus, speed test control instructions and data connection instructions for the apparatus to perform a high-speed test associated with network traffic of a network;
forwarding, by the at least one hardware processor, the speed test control instructions and the data connection instructions to a speed test control server;
establishing, by a hardware-based traffic analyzer in the apparatus, based on the speed test control instructions and the data connection instructions forwarded to the speed test control server, a connection between a data port of the hardware-based traffic analyzer and the speed test control server;
performing, by the hardware-based traffic analyzer, the high-speed test associated with the network traffic of the network by transmitting and receiving, via the data port of the hardware-based traffic analyzer, relatively high bit-rate data to and from the speed test control server;
receiving, by the at least one hardware processor, results of the high-speed test from the speed test control server;
transmitting, by the at least one hardware processor, the results of the high-speed test to the speed test control application; and
transmitting, via a control port of the hardware-based traffic analyzer, relatively slow-speed control traffic to the speed test control application.
7. The method according to claim 6 , wherein the speed test control server is located in a Cloud environment.
8. The method according to claim 6 , wherein the high-speed test is an uploaded and downloaded high-speed test.
9. The method according to claim 6 , further comprising:
implementing the speed test control application by a central processing unit (CPU) of the apparatus.
10. The method according to claim 6 , wherein the hardware-based traffic analyzer is implemented to include a Field Programmable Gate Array (FPGA) to handle the relatively high bit-rate data.
11. The method according to claim 6 , further comprising:
utilizing, by the at least one hardware processor, Transmission Control Protocol/Internet Protocol (TCP/IP) to transmit and receive the relatively high bit-rate data between the speed test control server and the hardware-based traffic analyzer.
12. A non-transitory computer readable medium storing machine readable instructions, the machine readable instructions, when executed by at least one hardware processor in an apparatus, cause the at least one hardware processor to:
receive, from a speed test control application installed on the apparatus, speed test control instructions and data connection instructions for the apparatus to perform a high-speed test associated with network traffic of a network;
forward the speed test control instructions and the data connection instructions to a speed test control server;
cause a hardware-based traffic analyzer to, based on the speed test control instructions and the data connection instructions forwarded to the speed test control server, establish a connection between a data port of the hardware-based traffic analyzer and the speed test control served;
cause the hardware-based traffic analyzer to perform the high-speed test associated with the network traffic of the network by transmitting and receiving, via the data port of the hardware-based traffic analyzer, relatively high bit-rate data to and from the speed test control server;
receive results of the high-speed test associated with the network traffic from the speed test control server;
transmit the results of the high-speed test to the speed test control application; and
cause the hardware-based traffic analyzer to transmit, via a control port of the hardware-based traffic analyzer, relatively slow-speed control traffic to the speed test control application.
13. The non-transitory computer readable medium according to claim 12 , wherein the high-speed test is an uploaded and downloaded high-speed test.
14. The non-transitory computer readable medium according to claim 12 , wherein the speed test control server is located in a Cloud environment.
15. The non-transitory computer readable medium according to claim 12 , wherein the hardware-based traffic analyzer is implemented to include a Field Programmable Gate Array (FPGA) to handle the relatively high bit-rate data.