Semiconductor memory device
The present disclosure provides a semiconductor memory device. The semiconductor memory device comprises a substrate, which includes a storage area and a peripheral area, wherein the storage area has a contact plug, a bit line structure adjacent to the contact plug, an air gap between the bit line structure and the contact plug, a barrier layer conformally overlaying the bit line structure, and a landing pad above the barrier layer, wherein the substrate includes a trench between the storage area and the peripheral area, the trench is filled with a nitride material, and the substrate further comprises a first oxide layer above the nitride material in the trench and on the landing pad, a nitride layer above the first oxide layer, and a second layer above the nitride layer.
1. A semiconductor memory device, comprising:
a substrate, which has a storage area and a peripheral area, wherein the storage area has a contact plug,
a bit line structure adjacent to the contact plug,
an air gap between the bit line structure and the contact plug,
a barrier layer conformally overlaying the bit line structure, and
a landing pad above the barrier layer,
wherein the substrate comprises:
a trench between the storage area and the peripheral area;
a nitride material being filled in the trench at a position that a top surface of the nitride material is coplanar with a top surface of the trench;
a first oxide layer formed above the nitride material in the trench and on the landing pad at a position that a bottom surface of the first oxide layer is in direct contact with the top surfaces of the trench and the nitride material;
a nitride layer formed above the first oxide layer at a position that a bottom surface of the nitride layer is in direct contact with a top surface of the first oxide layer; and
a second oxide layer formed above the nitride layer at a position that a bottom surface of the second oxide layer is in direct contact with a top surface of the nitride layer.
2. The semiconductor memory device according to claim 1 , wherein the substrate is selected from the group consisting of a silicon substrate, a gallium arsenide substrate, a silicon germanium substrate, a ceramic substrate, a quartz substrate, a glass substrate for a display, and a silicon-on-insulator (SOI) substrate.
3. The semiconductor memory device according to claim 1 , wherein the bit line structure comprises a bit line contact plug, a conductive pattern above the bit line contact plug at a position that a bottom of the conductive pattern is in direct contact with a top of the bit line contact plug, and a bit line isolating layer above the conductive pattern.
4. The semiconductor memory device according to claim 1 , wherein the substrate further comprises a pair of bit line spacers along the sidewalls of the bit line structure.
5. The semiconductor memory device according to claim 1 , wherein the substrate further comprises a pair of contact plug spacers along the sidewalls of the contact plug.
6. The semiconductor memory device according to claim 1 , wherein the nitride material for filling the trench is silicon nitride.
7. The semiconductor memory device according to claim 1 , wherein the first oxide layer is a silicon oxide layer.
8. The semiconductor memory device according to claim 1 , wherein the nitride layer is a silicon nitride layer.
9. The semiconductor memory device according to claim 1 , wherein the second oxide layer is a silicon oxide layer, wherein the first oxide layer, the nitride layer, and the second oxide layer have different thicknesses.