Auto-detection of interconnect hangs in integrated circuits
A self-detection mechanism for an IC is disclosed that determines whether the IC's internal bus is in a hanging state. An initialization sequence can be modified after a soft reset by reading data from an internal DRAM of the IC using a Direct Memory Access (DMA) controller as part of the initialization sequence. The read command is issued over the internal bus and, if the bus is hanging, the read command is not completed. Monitoring can be performed by waiting a predetermined period of time (e.g., 100 ms) to determine if the read was properly completed. If so, no further action is needed. If the read was not completed, then a hard reset is requested to be performed. Thus, an initialization sequence can be modified to run dummy transactions through the internal bus, and validate that all paths are functional.
1. An Integrated Circuit (IC), comprising:
a Direct Memory Access (DMA) controller;
a memory coupled to the DMA through a bus internal to the IC; and
a memory element within the memory or external to the memory coupled to the DMA controller, the memory element for indicating whether a hard reset of the IC is needed, wherein the IC is configured to set the memory element after a faux transaction on the bus fails to complete subsequent to a soft reset of the IC.
2. The IC of claim 1 , wherein the IC is coupled to a processor, which is configured for reading the memory element and generating the hard reset in response to the memory element being set.
3. The IC of claim 1 , wherein the IC is positioned within a server computer and is part of a Solid State Drive (SSD).
4. The IC of claim 3 , wherein the IC is further positioned on a daughter card plugged into the server computer.
5. The IC of claim 3 , wherein the hard reset is configured to be initiated by a processor on a motherboard within the server computer.
6. The IC of claim 1 , wherein the bus is an Advanced Extensible Interface (AXI) bus.
7. The IC of claim 1 , wherein the IC further includes a Peripheral Component Interconnect Express (PCIe) core for coupling to a PCIe bus.
8. The IC of claim 7 , wherein the soft reset resets the PCIe core without cycling power on the IC.
9. The IC of claim 1 , wherein the faux transaction is a read of the memory using the DMA controller.
10. The IC of claim 1 , wherein the hard reset cycles power so as to reset hardware and firmware on the IC.
11. An Integrated Circuit (IC), comprising:
a Direct Memory Access (DMA) controller;
a memory coupled to the DMA through a bus internal to the IC; and
wherein the DMA controller is configured to transmit a faux transaction to the memory on the bus subsequent to a soft reset to test whether the bus is in a hung state.
12. The IC of claim 11 , wherein the DMA controller is configured to set a memory element within the memory or external to the memory if the faux transaction fails.
13. The IC of claim 12 , wherein the memory element is coupled to a processor within a server computer and the IC is configured to alert the processor that a hard reset is needed if the faux transaction fails through the setting of the memory element.
14. The IC of claim 11 , wherein the faux transaction is configured to occur after the soft reset of the IC.
15. The IC of claim 11 , wherein the soft reset is configured to restart software running on the IC without cycling power to the IC.
16. The IC of claim 11 , wherein the IC further includes a Peripheral Component Interconnect Express (PCIe) core for coupling to a PCIe bus.
17. An Integrated Circuit (IC), comprising:
a Direct Memory Access (DMA) controller;
a memory coupled to the DMA through a bus internal to the IC; and
a memory element coupled to the DMA controller, wherein the IC is configured to set the memory element after a faux transaction on the bus fails to complete subsequent to a soft reset of the IC for indicating that a hard reset of the IC is needed.
18. The IC of claim 17 , wherein the memory element is within the memory or external to the memory.
19. The IC of claim 17 , wherein the faux transaction includes a read of the memory from the DMA controller.
20. The IC of claim 17 , wherein the internal bus is an Advanced Extensible Interface (AXI) bus and the IC is coupled to a processor via a Peripheral Component Interconnect Express (PCIe) bus.