High performance high voltage isolators

1. An integrated circuit, comprising;

a semiconductor substrate;

a plurality of dielectric layers over the semiconductor substrate, including a top dielectric layer;

a metal plate over the top dielectric layer;

a metal ring over the top dielectric layer and substantially surrounding the metal plate;

a protective overcoat directly vertically overlying the metal ring and overlying the metal plate; and

a trench opening through the protective overcoat, the trench opening exposing the top dielectric layer between the metal plate and the metal ring, the trench opening substantially surrounding the metal plate.

2. The integrated circuit of claim 1 in which the metal plate and the metal ring are formed of aluminum and are located on the top dielectric layer.

3. The integrated circuit of claim 2 in which the protective overcoat includes a dielectric liner overlying the metal ring and overlying the metal plate, and a dielectric overcoat located on the dielectric liner, the dielectric overcoat including a silicon nitride-related material selected from the group consisting of silicon nitride, silicon oxynitride, silicon-rich silicon nitride, silicon-rich silicon oxynitride, silicon oxide carbide nitride, and silicon carbide nitride.

4. The integrated circuit of claim 1 in which the metal plate and the metal ring include copper and are located within the top dielectric layer.

5. The integrated circuit of claim 4 in which the protective overcoat includes a dielectric liner overlying the metal ring and overlying the metal plate and a dielectric overcoat located on the dielectric liner, the dielectric liner including a first silicon nitride-related material that is selected from the group consisting of silicon nitride, silicon oxynitride, silicon-rich silicon nitride, silicon-rich silicon oxynitride, silicon oxide carbide nitride, and silicon carbide nitride.

6. The integrated circuit of claim 1 in which the metal ring is conductively connected to the semiconductor substrate; the metal plate is a top metal plate; and the integrated circuit includes a bottom metal plate located directly between the top metal plate and the semiconductor substrate.

7. The integrated circuit of claim 1 including a contact opening through the protective overcoat, the contact opening exposing the metal plate.

8. An integrated circuit, comprising;

a semiconductor substrate;

a top metal plate, and a bottom metal plate between the top metal plate and the semiconductor substrate;

a plurality of dielectric layers between the top and bottom metal plates, including a top dielectric layer under and touching the top metal plate;

a dielectric protective overcoat that covers the top dielectric layer and extends over the top metal plate; and

a trench opening that surrounds the top metal plate and extends through the dielectric protective overcoat and stops on the top dielectric layer.

9. The integrated circuit of claim 8 , further comprising a ground ring that substantially surrounds the top and bottom metal plates, the ground ring including a top metal ring over and touching the top dielectric layer, the trench opening between the top metal plate and the top metal ring.

10. The integrated circuit of claim 9 , wherein the ground ring is electrically connected to the semiconductor substrate between first and second trench isolation regions.

11. The integrated circuit of claim 8 , wherein the bottom metal plate includes aluminum.

12. The integrated circuit of claim 8 , wherein the dielectric protective overcoat includes silicon and nitrogen.

13. The integrated circuit of claim 8 , wherein the dielectric protective overcoat includes a dielectric liner and a dielectric overcoat over the dielectric liner, the dielectric overcoat comprising silicon nitride.

14. The integrated circuit of claim 8 , wherein the top and bottom metal plates are vertically spaced apart by 14 - 18 μm.

15. The integrated circuit of claim 8 , wherein the plurality of dielectric layers includes a plurality of silicon oxide layers.

16. An integrated circuit, comprising;

a semiconductor substrate;

a top metal plate, and a bottom metal plate between the top metal plate and the semiconductor substrate;

a plurality of dielectric layers between the top and bottom metal plates, including a top dielectric layer under and touching the top metal plate;

a metal ring over and touching the top dielectric layer, the metal ring substantially surrounding the top metal plate;

a dielectric protective overcoat that covers the top dielectric layer and extends over the top metal plate and over the metal ring; and

a trench opening between the top metal plate and the metal ring, the trench opening extending through the dielectric protective overcoat.

17. The integrated circuit of claim 16 , wherein the trench opening surrounds the top metal plate.

18. The integrated circuit of claim 16 , wherein the trench opening stops on the top dielectric layer.

19. The integrated circuit of claim 16 , wherein the metal ring is a top metal ring of a stacked ground ring structure that is electrically connected to the semiconductor substrate.

20. The integrated circuit of claim 19 , wherein the metal ring is electrically connected to the semiconductor substrate between first and second dielectric isolation regions.

21. The integrated circuit of claim 16 , wherein the dielectric protective overcoat includes a dielectric liner between a dielectric overcoat and the top dielectric layer.

22. The integrated circuit of claim 21 , wherein the dielectric liner includes silicon oxide and the dielectric overcoat comprises silicon and nitrogen.

23. The integrated circuit of claim 22 , wherein the dielectric overcoat is selected from the group consisting of silicon nitride, silicon oxynitride, silicon-rich silicon nitride, silicon-rich silicon oxynitride, silicon oxide carbide nitride, and silicon carbide nitride.