IP Library Granted Patent US 11,881,513
Granted Patent B2
US 11,881,513 · App. 17/047,724 · Granted Jan 23, 2024

Semiconductor device

Inventors: Kosei Nei (Yokohama, JP); Tsutomu Murakawa (Isehara, JP); Toshihiko Takeuchi (Atsugi, JP); Kentaro Sugaya (Atsugi, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/24H01L27/1225H10B12/312
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Quick Facts
Patent No.
US 11,881,513
App. No.
17/047,724
Granted
Jan 23, 2024
Kind
B2
Abstract

A semiconductor device that can be scaled down or highly integrated is provided. The semiconductor device includes a first layer and a second layer over the first layer. The first layer and the second layer each include a transistor. The transistor in the first layer and the transistor in the second layer each include a first oxide, a first conductor and a second conductor over the first oxide, a first insulator placed to cover the first conductor, the second conductor, and the first oxide, a second insulator over the first insulator, a second oxide placed between the first conductor and the second conductor over the first oxide, a third insulator over the second oxide, a third conductor over the third insulator, and a fourth insulator in contact with a top surface of the second insulator, a top surface of the second oxide, a top surface of the third insulator, and a top surface of the third conductor. The first insulator and the fourth insulator are less likely than the second insulator to allow oxygen to pass through.

Claims (62)

1. A semiconductor device comprising:

a first layer and a second layer over the first layer,

wherein the first layer and the second layer each comprise a transistor,

wherein the transistor in the first layer and the second layer comprises:

a first oxide;

a first conductor and a second conductor over the first oxide;

a first insulator placed to cover the first conductor, the second conductor, and the first oxide;

a second insulator over the first insulator;

a second oxide placed between the first conductor and the second conductor over the first oxide;

a third insulator over the second oxide;

a third conductor over the third insulator; and

a fourth insulator in contact with a top surface of the second insulator, a top surface of the second oxide, a top surface of the third insulator, and a top surface of the third conductor, and

wherein the first insulator and the fourth insulator are oxides comprising one or both of aluminum and hafnium.

2. The semiconductor device according to claim 1 ,

wherein the first oxide and the second oxide comprise In, an element M, and Zn, and

wherein M is Al, Ga, Y, or Sn.

3. The semiconductor device according to claim 1 , further comprising a third layer placed below the first layer,

wherein the third layer comprises:

a fifth insulator over a silicon substrate; and

a fourth conductor over the fifth insulator.

4. The semiconductor device according to claim 1 , further comprising a fifth insulator and a sixth insulator,

wherein the fifth insulator is placed below the first oxide and the first insulator, and

wherein the sixth insulator is placed below the fifth insulator.

5. The semiconductor device according to claim 4 , further comprising a fourth conductor,

wherein the fourth conductor is placed below the sixth insulator to overlap with the first oxide.

6. The semiconductor device according to claim 1 ,

wherein the second oxide has crystallinity.

7. The semiconductor device according to claim 6 ,

wherein the second oxide comprises a region in contact with a side surface of the second insulator, the region in which a c-axis is oriented substantially perpendicular to the side surface.

8. The semiconductor device according to claim 6 ,

wherein a third oxide is placed over and in contact with the second oxide.

9. A semiconductor device comprising:

a first layer and a second layer over the first layer,

wherein the first layer and the second layer each comprise a transistor,

wherein the transistor in the first layer and the second layer comprises:

a first oxide;

a first conductor and a second conductor over the first oxide;

a first insulator placed to cover the first conductor, the second conductor, and the first oxide;

a second insulator over the first insulator;

a second oxide placed between the first conductor and the second conductor over the first oxide;

a third insulator over the second oxide;

a third conductor over the third insulator; and

a fourth insulator in contact with a top surface of the second insulator, a top surface of the second oxide, a top surface of the third insulator, and a top surface of the third conductor, and

wherein each of the first insulator and the fourth insulator comprises any one of aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, silicon nitride oxide, and silicon nitride.

10. The semiconductor device according to claim 9 ,

wherein the first oxide and the second oxide comprise In, an element M, and Zn, and

wherein M is Al, Ga, Y, or Sn.

11. The semiconductor device according to claim 9 , further comprising a third layer placed below the first layer,

wherein the third layer comprises:

a fifth insulator over a silicon substrate; and

a fourth conductor over the fifth insulator.

12. The semiconductor device according to claim 9 , further comprising a fifth insulator and a sixth insulator,

wherein the fifth insulator is placed below the first oxide and the first insulator, and

wherein the sixth insulator is placed below the fifth insulator.

13. The semiconductor device according to claim 12 , further comprising a fourth conductor,

wherein the fourth conductor is placed below the sixth insulator to overlap with the first oxide.

14. The semiconductor device according to claim 9 ,

wherein the second oxide has crystallinity.

15. The semiconductor device according to claim 14 ,

wherein the second oxide comprises a region in contact with a side surface of the second insulator, the region in which a c-axis is oriented substantially perpendicular to the side surface.

16. The semiconductor device according to claim 14 ,

wherein a third oxide is placed over and in contact with the second oxide.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 15, 2020
From: NEI, KOSEI; MURAKAWA, TSUTOMU; TAKEUCHI, TOSHIHIKO; SUGAYA, KENTARO
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 054060/0699 →
Priority Claims (1)
JP 2018-086578 · Apr 27, 2018 · national
Continuity (1)
Related Publication 20210167174A1 · Jun 3, 2021