Calibration scheme for filling lookup table in an ADC

1. A circuit comprising:

a calibration engine configured to generate a plurality of input codes;

a digital to analog converter (DAC) coupled to the calibration engine, and configured to generate a first calibration signal in response to a first input code of the plurality of input codes;

an analog to digital converter (ADC) coupled to the DAC and configured to generate a plurality of raw codes responsive to the first calibration signal; and

a storage circuit coupled to the ADC and configured to store a first output code corresponding to the first input code, the first output code is obtained using the plurality of raw codes generated by the ADC.

2. The circuit of claim 1 , wherein the calibration engine is configured to store the plurality of raw codes corresponding to the first input code, and the first output code stored in the storage circuit is average of the plurality of raw codes.

3. The circuit of claim 1 , wherein the plurality of input codes includes the first input code and a second input code, and a difference between the first input code and the second input code is M, where M is an integer.

4. The circuit of claim 3 wherein the first output code corresponding to the first input code is stored in a first location in the storage circuit, and a second output code corresponding to the second input code is stored in a second location in the storage circuit.

5. The circuit of claim 4 , wherein when the second output code is less than a predetermined threshold, the second output code is incremented by defined bits and stored in a third location in the storage circuit.

6. The circuit of claim 1 further comprising a multiplexer coupled to the DAC and configured to provide one of an input voltage and the first calibration signal to the ADC.

7. The circuit of claim 6 , wherein the ADC further comprises:

a plurality of preamplifiers, each preamplifier configured to compare one of the input voltage and the first calibration signal to a threshold voltage;

a delay multiplexer coupled to the plurality of preamplifiers and configured to generate a delay signal based on an output of one of the preamplifiers; and

a backend ADC configured to generate a first raw code in response to the delay signal.

8. The circuit of claim 6 , wherein each preamplifier has a different threshold voltage.

9. The circuit of claim 8 configured to operate in a mission mode, wherein in the mission mode:

the multiplexer is configured to provide the input voltage; and

the ADC is configured to generate a raw code in response to the input voltage, wherein an output code in the storage circuit corresponding to the raw code is generated as a final output.

10. The circuit of claim 8 , wherein the plurality of preamplifiers includes a first preamplifier and a second preamplifier, the first and second preamplifiers have successive threshold voltages.

11. The circuit of claim 10 , wherein:

the first preamplifier is activated;

the storage circuit is configured to store M+L output codes corresponding to M+L input codes processed through the first preamplifier, the first preamplifier toggles at Mth input code, and M and L are positive integers;

the first preamplifier is inactivated and the second preamplifier is activated;

the input code is changed to M−L+1; and

the storage circuit is configured to store output codes corresponding to each input code from (M−L+1)th input code processed through the second preamplifier.

12. The circuit of claim 10 , wherein:

the first preamplifier is activated;

the storage circuit is configured to store M+T output codes corresponding to M+T input codes processed through the first preamplifier, the first preamplifier toggles at Mth input code and the raw code saturates at Tth input code;

the first preamplifier is inactivated and the second preamplifier is activated;

the input code is decremented from Tth input code to Dth input code, wherein the raw code saturates at Dth input code, where M, T and D are integers; and

the storage circuit is configured to store output codes corresponding to each input code from Dth input code.

13. The circuit of claim 10 , wherein:

the first preamplifier is activated;

the storage circuit is configured to store M+L output codes corresponding to M+L input codes processed through the first preamplifier, the first preamplifier toggles at Mth input code, and M and L are integers;

the first preamplifier is inactivated and the second preamplifier is activated;

the input code is changed to M−L+1;

the storage circuit is configured to store output codes corresponding to each input code from (M−L+1)th input code processed through the second preamplifier;

a discontinuity parameter is estimated from the output codes generated through the first preamplifier from Mth input code to Lth input code and the output codes generated through the second preamplifier from Lth input code to the Mth input code; and

the discontinuity parameter is added to output codes generated through the second and successive preamplifiers, when the discontinuity parameter is greater than a first threshold.

14. A method of calibration comprising:

generating a plurality of input codes;

generating a first calibration signal by a digital to analog converter (DAC) in response to a first input code of the plurality of input codes;

generating a plurality of raw codes by an analog to digital converter (ADC) responsive to the first calibration signal, the ADC coupled to the DAC; and

storing a first output code in a storage circuit corresponding to the first input code, the first output code is obtained using the plurality of raw codes.

15. The method of claim 14 , wherein the first output code is average of the plurality of raw codes.

16. The method of claim 14 , wherein the plurality of input codes includes the first input code and a second input code, and a difference between the first input code and the second input code is M, where M is an integer.

17. The method of claim 16 further comprising:

storing the first output code corresponding to the first input code in a first location in a storage circuit;

storing a second output code corresponding to a second input code in a second location in the storage circuit; and

incrementing the second output code by defined bits when the second output code is less than a predetermined threshold and storing the second output code in a third location in the storage circuit.

18. The method of claim 17 further comprising:

providing an input voltage to the ADC;

generating a raw code by the ADC responsive to the input voltage; and

generating an output code as a final output, the output code corresponds to the raw code and stored in the storage circuit coupled to the ADC.

19. The method of claim 17 further comprising:

activating a first preamplifier, the ADC includes the first preamplifier and a second preamplifier, the first and second preamplifiers have successive threshold voltages;

processing M+L input codes through the first preamplifier, where M and L are integers;

storing M+L output codes corresponding to M+L input codes, the first preamplifier toggles at Mth input code;

inactivating the first preamplifier and activating the second preamplifier;

modifying the input code to M−L+1; and

storing output codes corresponding to each input code from (M−L+1)th input code processed through the second preamplifer.

20. The method of claim 19 further comprising:

activating the first preamplifier;

storing M+T output codes corresponding to M+T input codes processed through the first preamplifier, the first preamplifier toggles at Mth input code and the raw code saturates at Tth input code;

inactivating the first preamplifier and activating the second preamplifier;

decrementing the input code from Lth input code to Dth input code, wherein the raw code saturates at Dth input code, where M, T and D are integers; and

storing output codes corresponding to each input code from Dth input code.

21. The method of claim 19 further comprising:

activating a first preamplifier, the ADC includes the first preamplifier and a second preamplifier, the first and second preamplifiers have successive threshold voltages;

processing M+L input codes through the first preamplifier, where M and L are integers;

storing M+L output codes corresponding to M+L input codes, the first preamplifier toggles at Mth input code;

inactivating the first preamplifier and activating the second preamplifier;

modifying the input code to M−L+1;

storing output codes corresponding to each input code from (M−L+1)th input code processed through the second preamplifier;

estimating a discontinuity parameter from the output codes generated through the first preamplifier from Mth input code to Lth input code and the output codes generated through the second preamplifier from Lth input code to the Mth input code; and

adding the discontinuity parameter to output codes generated through the second and successive preamplifiers, when the discontinuity parameter is greater than a first threshold.

22. A device comprising:

a processor;

a memory module coupled to the processor; and

a circuit coupled to the processor and the memory module, the circuit comprising:

a calibration engine configured to generate a plurality of input codes;

a digital to analog converter (DAC) coupled to the calibration engine, and configured to generate a first calibration signal in response to a first input code of the plurality of input codes;

an analog to digital converter (ADC) coupled to the DAC and configured to generate a plurality of raw codes responsive to the first calibration signal; and

a storage circuit coupled to the ADC and configured to store a first output code corresponding to the first input code, the first output code is obtained using the plurality of raw codes generated by the ADC.