Method and storage device for improving NAND flash memory performance for intensive read workloads

1. A method for reading data in a storage device, the method comprising:

receiving, by the storage device, a read command from a host device, wherein the read command comprises a Logical Block Address (LBA) of stored data to be read;

obtaining, by the storage device, a Physical Block Number (PBN) based on the LBA and a Logical to Physical (L2P) mapping;

determining, by the storage device, whether the PBN is a block of a volatile memory of the storage device;

reading, by the storage device, the stored data directly from the volatile memory based on the PBN being a block of the volatile memory;

incrementing, by the storage device, a read counter associated with the PBN based on the stored data being read directly from the volatile memory;

reading, by the storage device, the stored data from a non-volatile memory of the storage device based on the PBN not being a block of the volatile memory; and

determining, by the storage device, whether a read disturbance exceeds a threshold limit and whether the read counter exceeds a maximum read limit while the stored data is read from the non-volatile memory.

2. The method as claimed in claim 1 , further comprising:

reading, by the storage device, the stored data from the non-volatile memory based on the read disturbance not exceeding the threshold limit while the stored data is read from the non-volatile memory; and

allocating, by the storage device, a buffer in the volatile memory based on the read disturbance exceeding the threshold limit while the stored data is read from the non-volatile memory.

3. The method as claimed in claim 2 , wherein the stored data comprises parity bits, and

wherein the threshold limit is a maximum number of bits for correction using the parity bits.

4. The method as claimed in claim 2 , wherein the allocating the buffer in the volatile memory further comprises:

determining, by the storage device, whether the buffer in the volatile memory has been successfully allocated;

relocating, by the storage device, the stored data from the non-volatile memory to the volatile memory based on the allocating of the buffer in the volatile memory being successful;

updating the L2P mapping based on the stored data being relocated to the volatile memory;

reading the stored data from the volatile memory; and

relocating data from the volatile memory to the non-volatile memory based on the allocating of the buffer in the volatile memory not being successful, wherein the relocated data comprises a lowest read counter among a plurality of read counters of the volatile memory.

5. The method as claimed in claim 4 , wherein the relocating the data from the volatile memory to the non-volatile memory comprises:

identifying, by the storage device, the buffer based on the buffer corresponding to the lowest read counter in the volatile memory;

allocating, by the storage device, a block of a Single-level cell (SLC) NAND flash memory in the non-volatile memory to store the data;

relocating, by the storage device, the data in the SLC NAND flash memory; and

updating the PBN associated with the data to indicate the block of the SLC NAND flash memory.

6. The method as claimed in claim 1 , further comprising:

reading, by the storage device, the stored data from the non-volatile memory based on the read counter not exceeding the maximum read limit while the stored data is read from the non-volatile memory; and

allocating, by the storage device, a buffer in the volatile memory based on the read counter exceeding the maximum read limit while the stored data is read from the non-volatile memory.

7. The method as claimed in claim 1 , wherein the L2P mapping indicates an actual physical location for each LBA in the storage device.

8. A storage device comprising:

a volatile memory;

a non-volatile memory; and

a storage device controller, operably connected to the volatile memory and the non-volatile memory, configured to:

receive a read command from a host device, wherein the read command comprises a Logical Block Address (LBA) of stored data to be read;

obtain a Physical Block Number (PBN) based on the LBA and a Logical to Physical (L2P) mapping;

determine whether the PBN is a block of the volatile memory;

read the stored data directly from the volatile memory based on the PBN being a block of the volatile memory;

increment a read counter associated with the PBN based on the stored data being read directly from the volatile memory;

read the stored data from the non-volatile memory based on the PBN not being a block of the volatile memory; and

determine whether a read disturbance exceeds a threshold limit and whether the read counter exceeds a maximum read limit while the stored data is read from the non-volatile memory.

9. The storage device as claimed in claim 8 , wherein the storage device controller is further configured to:

read the stored data from the non-volatile memory based on the read disturbance not exceeding the threshold limit while the stored data is read from the non-volatile memory; and

allocate a buffer in the volatile memory based on the read disturbance exceeding the threshold limit while the stored data is read from the non-volatile memory.

10. The storage device as claimed in claim 9 , wherein the stored data comprises parity bits, and

wherein the threshold limit is a maximum number of bits for correction using the parity bits.

11. The storage device as claimed in claim 9 , wherein the storage device controller is further configured to:

determine whether the buffer in the volatile memory has been successfully allocated;

relocate the stored data from the non-volatile memory to the volatile memory based on allocation of the buffer in the volatile memory being successful;

update the L2P mapping based on the stored data being relocated to the volatile memory;

read the stored data from the volatile memory;

relocate data from the volatile memory to the non-volatile memory based on allocation of the buffer in the volatile memory not being successful, wherein the relocated data comprises a lowest read counter from among a plurality of read counters of the volatile memory;

read the stored data from the non-volatile memory based on the read counter not exceeding the maximum read limit while the stored data is read from the non-volatile memory; and

allocate the buffer in the volatile memory based on the read counter exceeding the maximum read limit while the stored data is read from the non-volatile memory.

12. The storage device as claimed in claim 11 , wherein the storage device controller is further configured to:

identify the buffer based on the buffer corresponding to the lowest read counter in the volatile memory;

allocate a block of a Single-level cell (SLC) NAND flash memory in the non-volatile memory to store the data;

relocate the data in the SLC NAND flash memory; and

update the PBN associated with the data to indicate the block of the SLC NAND flash memory.

13. The storage device as claimed in claim 8 , wherein the storage device controller is further configured to:

read the stored data from the non-volatile memory based on the read counter not exceeding the maximum read limit while the stored data is read from the non-volatile memory; and

allocate a buffer in the volatile memory based on the read counter exceeding the maximum read limit while the stored data is read from the non-volatile memory.

14. The storage device as claimed in claim 8 , wherein the L2P mapping indicates an actual physical location for each LBA in the storage device.

15. A storage device controller comprising:

at least one processor configured to:

receive a read command from a host device, wherein the read command comprises a Logical Block Address (LBA) of stored data to be read;

obtain a Physical Block Number (PBN) based on the LBA and a Logical to Physical (L2P) mapping;

determine whether the PBN is a block of a volatile memory of a storage device;

read the stored data directly from the volatile memory based on the PBN being a block of the volatile memory;

increment a read counter associated with the PBN based on the stored data being read directly from the volatile memory;

read the stored data from a non-volatile memory of the storage device based on the PBN not being a block of the volatile memory; and

determine whether a read disturbance exceeds a threshold limit and whether the read counter exceeds a maximum read limit while the stored data is read from the non-volatile memory.

16. The storage device controller as claimed in claim 15 , wherein the at least one processor is further configured to:

read the stored data from the non-volatile memory based on the read disturbance not exceeding the threshold limit while the stored data is read from the non-volatile memory;

allocate a buffer in the volatile memory based on the read disturbance exceeding the threshold limit while the stored data is read from the non-volatile memory;

read the stored data from the non-volatile memory based on the read counter not exceeding the maximum read limit while the stored data is read from the non-volatile memory; and

allocate the buffer in the volatile memory based on the read counter exceeding the maximum read limit while the stored data is read from the non-volatile memory.

17. The storage device controller as claimed in claim 16 , wherein the stored data comprises parity bits, and

wherein the threshold limit is a maximum number of bits for correction using the parity bits.

18. The storage device controller as claimed in claim 15 , wherein the at least one processor is further configured to:

read the stored data from the non-volatile memory based on the read disturbance not exceeding the threshold limit while the stored data is read from the non-volatile memory;

determine whether a buffer in the volatile memory has been successfully allocated;

relocate the stored data from the non-volatile memory to the volatile memory based on allocation of the buffer in the volatile memory being successful;

update the L2P mapping based on the stored data being relocated to the volatile memory;

read the stored data from the volatile memory; and

relocate data from the volatile memory to the non-volatile memory based on allocation of the buffer in the volatile memory not being successful, wherein the relocated data comprises a lowest read counter from among a plurality of read counters of the volatile memory.

19. The storage device controller as claimed in claim 18 , wherein the at least one processor is further configured to:

identify the buffer based on the buffer corresponding to the lowest read counter in the volatile memory;

allocate a block of a Single-level cell (SLC) NAND flash memory in the non-volatile memory to store the data;

relocate the data in the SLC NAND flash memory; and

update the PBN associated with the data to indicate the block of the SLC NAND flash memory.

20. The storage device controller as claimed in claim 15 , wherein the storage device controller is further configured to:

read the stored data from the non-volatile memory based on the read counter not exceeding the maximum read limit while the stored data is read from the non-volatile memory; and

allocate a buffer in the volatile memory based on the read counter exceeding the maximum read limit while the stored data is read from the non-volatile memory.