Systems and methods for performing nibble-sized operations on matrix elements
Disclosed embodiments relate to systems and methods for performing nibble-sized operations on matrix elements. In one example, a processor includes fetch circuitry to fetch an instruction, decode circuitry to decode the fetched instruction the fetched instruction having fields to specify an opcode and locations of first source, second source, and destination matrices, the opcode to indicate the processor is to, for each pair of corresponding elements of the first and second source matrices, logically partition each element into nibble-sized partitions, perform an operation indicated by the instruction on each partition, and store execution results to a corresponding nibble-sized partition of a corresponding element of the destination matrix. The exemplary processor includes execution circuitry to execute the decoded instruction as per the opcode.
1. A processor comprising:
fetch circuitry to fetch a single instruction;
decode circuitry to decode the fetched single instruction having fields to specify an opcode, locations of first source, second source, and destination matrices that are each a single two-dimensional tile register in a matrix operations accelerator of the processor, and that an element size of each element of the first source, the second source, and the destination matrices is larger than a nibble, the opcode to indicate execution circuitry is to cause a grid of fused multiply and accumulate circuits of the matrix operations accelerator to, for each pair of corresponding elements of the first and second source matrices, logically partition each element into nibble-sized partitions, perform an operation indicated by the single instruction on each partition, and store execution results to a corresponding nibble-sized partition of a corresponding element of the destination matrix; and
the execution circuitry to execute the decoded single instruction as per the opcode.
2. The processor of claim 1 , wherein the operation is one of addition, subtraction, and multiplication.
3. The processor of claim 1 , wherein the operation is a logical operation to be performed by the execution circuitry in bitwise fashion.
4. The processor of claim 1 , wherein the operation is indicated by an additional instruction field.
5. The processor of claim 1 , wherein the operation is indicated as part of the opcode.
6. The processor of claim 1 , wherein the single instruction is further to specify a multi-bit writemask having a plurality of bits to control whether to mask each element of the destination matrix, wherein masked destination elements are either to be zeroed or merged.
7. The processor of claim 1 , wherein the single instruction is further to specify the element size of each element of the first source, the second source, and the destination matrices is one of 8 bits, 16 bits, 32 bits, 64 bits, or 128 bits.
8. A method to be performed by a processor, the method comprising:
fetching, using fetch circuitry, a single instruction;
decoding, using decode circuitry, the fetched single instruction having fields to specify an opcode, locations of first source, second source, and destination matrices that are each a single two-dimensional tile register in a matrix operations accelerator of the processor, and that an element size of each element of the first source, the second source, and the destination matrices is larger than a nibble, the opcode to indicate execution circuitry is to cause a grid of fused multiply and accumulate circuits of the matrix operations accelerator to, for each pair of corresponding elements of the first and second source matrices, logically partition each element into nibble-sized partitions, perform an operation indicated by the single instruction on each partition, and store execution results to a corresponding nibble-sized partition of a corresponding element of the destination matrix; and
executing, using the execution circuitry, the decoded single instruction as per the opcode.
9. The method of claim 8 , wherein the operation is one of addition, subtraction, and multiplication.
10. The method of claim 8 , wherein the operation is a logical operation to be performed by the execution circuitry in bitwise fashion.
11. The method of claim 8 , wherein the operation is indicated by an additional instruction field.
12. The method of claim 8 , wherein the operation is indicated as part of the opcode.
13. The method of claim 8 , wherein the single instruction is further to specify a multi-bit writemask having a plurality of bits to control whether the execution circuitry is to mask each element of the destination matrix, wherein masked destination elements are either to be zeroed or merged.
14. The method of claim 8 , wherein the single instruction is further to specify the element size of each element of the first source, the second source, and the destination matrices is one of 8 bits, 16 bits, 32 bits, 64 bits, or 128 bits.
15. A non-transitory machine-readable medium containing code to be performed by a processor by:
fetching, using fetch circuitry, a single instruction;
decoding, using decode circuitry, the fetched single instruction having fields to specify an opcode, locations of first source, second source, and destination matrices that are each a single two-dimensional tile register in a matrix operations accelerator of the processor, and that an element size of each element of the first source, the second source, and the destination matrices is larger than a nibble, the opcode to indicate execution circuitry is to cause a grid of fused multiply and accumulate circuits of the matrix operations accelerator to, for each pair of corresponding elements of the first and second source matrices, logically partition each element into nibble-sized partitions, perform an operation indicated by the single instruction on each partition, and store execution results to a corresponding nibble-sized partition of a corresponding element of the destination matrix; and
executing, using the execution circuitry, the decoded single instruction as per the opcode.
16. The non-transitory machine-readable medium of claim 15 , wherein the operation is one of addition, subtraction, and multiplication.
17. The non-transitory machine-readable medium of claim 15 , wherein the operation is a logical operation to be performed by the execution circuitry in bitwise fashion.
18. The non-transitory machine-readable medium of claim 15 , wherein the single instruction is further to specify a multi-bit writemask having a plurality of bits to control whether to mask each element of the destination matrix, wherein masked destination elements are either to be zeroed or merged.
19. The non-transitory machine-readable medium of claim 15 , wherein the single instruction is further to specify the element size of each element of the first source, the second source, and the destination matrices is one of 8 bits, 16 bits, 32 bits, 64 bits, or 128 bits.