Memory devices

1. A memory device comprising:

a row decoder configured to generate a plurality of word line control signals, based on a row address received from an external device;

a first sub-array including a plurality of memory cells connected with a plurality of word lines;

a first sub-word line driver configured to provide a selection voltage or a non-selection voltage to odd-numbered word lines of the plurality of word lines, based on odd-numbered word line control signals corresponding to the odd-numbered word lines; and

a second sub-word line driver configured to provide the selection voltage or the non-selection voltage to even-numbered word lines of the plurality of word lines, based on even-numbered word line control signals corresponding to the even-numbered word lines,

wherein the first sub-word line driver is further configured to apply the non-selection voltage to non-selection word lines of the even-numbered word lines, in response to the even-numbered word line control signals, and

wherein the second sub-word line driver is further configured to apply the non-selection voltage to non-selection word lines of the odd-numbered word lines, in response to the odd-numbered word line control signals.

2. The memory device of claim 1 , wherein the odd-numbered word lines alternate with the even-numbered word lines in the first sub-array.

3. The memory device of claim 1 ,

wherein the plurality of word lines extend along a first direction,

wherein the first sub-word line driver, the first sub-array, and the second sub-word line driver are arranged along the first direction,

wherein the first sub-array is between the first sub-word line driver and the second sub-word line driver,

wherein the first sub-word line driver is connected to respective first ends of the plurality of word lines, and

wherein the second sub-word line driver is connected to respective second ends of the plurality of word lines that are opposite the first ends.

4. The memory device of claim 1 ,

wherein the first sub-word line driver includes:

a plurality of odd-numbered main driving circuits configured to apply the selection voltage or the non-selection voltage to the odd-numbered word lines in response to the odd-numbered word line control signals; and

a plurality of even-numbered supplementary driving circuits configured to selectively apply the non-selection voltage to the even-numbered word lines in response to the even-numbered word line control signals, and

wherein the second sub-word line driver includes:

a plurality of even-numbered main driving circuits configured to apply the selection voltage or the non-selection voltage to the even-numbered word lines in response to the even-numbered word line control signals; and

a plurality of odd-numbered supplementary driving circuits configured to selectively apply the non-selection voltage to the odd-numbered word lines in response to the odd-numbered word line control signals.

5. The memory device of claim 4 ,

wherein each of the plurality of odd-numbered main driving circuits includes:

an odd-numbered selection circuit connected to one corresponding word line of the odd-numbered word lines, and configured to selectively apply the selection voltage to the one corresponding word line in response to one of the odd-numbered word line control signals; and

an odd-numbered non-selection circuit connected to the one corresponding word line of the odd-numbered word lines, and configured to selectively apply the non-selection voltage to the one corresponding word line in response to the one of the odd-numbered word line control signals, and

wherein each of the plurality of even-numbered supplementary driving circuits includes:

an even-numbered selection circuit connected to one corresponding word line of the even-numbered word lines, and configured to selectively apply the non-selection voltage to the one corresponding word line of the even-numbered word lines in response to one of the even-numbered word line control signals.

6. The memory device of claim 1 , wherein each of the plurality of memory cells includes:

a selection transistor configured to operate in response to a corresponding word line of the plurality of word lines; and

a storage capacitor connected to the selection transistor.

7. The memory device of claim 6 , wherein the selection transistor includes a vertical channel transistor (VCT).

8. A memory device comprising:

a row decoder configured to generate a first word line selection signal, a first word line non-selection signal, a second word line selection signal, and a second word line non-selection signal, based on a row address received from an external device;

a first sub-array including a plurality of first memory cells connected to a first word line and a plurality of second memory cells connected to a second word line;

a first sub-word line driver connected to the first word line, and configured to apply a selection voltage to the first word line in response to the first word line selection signal and to apply a non-selection voltage to the first word line in response to the first word line non-selection signal; and

a second sub-word line driver connected to the second word line, and configured to apply the selection voltage to the second word line in response to the second word line selection signal and to apply the non-selection voltage to the second word line in response to the second word line non-selection signal,

wherein the first sub-word line driver is connected to the second word line and is further configured to apply the non-selection voltage to the second word line in response to the second word line non-selection signal, and

wherein the second sub-word line driver is connected to the first word line and is further configured to apply the non-selection voltage to the first word line in response to the first word line non-selection signal.

9. The memory device of claim 8 , wherein the first sub-array is between the first sub-word line driver and the second sub-word line driver.

10. The memory device of claim 8 ,

wherein each of the first word line and the second word line extends along a first direction,

and

wherein the first word line and the second word line are physically adjacent to each other along a second direction perpendicular to the first direction.

11. The memory device of claim 8 ,

wherein, when the first word line is a selection word line, the first sub-word line driver is configured to apply the selection voltage to the first word line and apply the non-selection voltage to the second word line, and the second sub-word line driver is configured to float the first word line and apply the non-selection voltage to the second word line, and

wherein, when the second word line is a selection word line, the first sub-word line driver is configured to apply the non-selection voltage to the first word line and float the second word line, and the second sub-word line driver is configured to apply the non-selection voltage to the first word line and apply the selection voltage to the second word line.

12. The memory device of claim 8 , wherein the first and second sub-word line drivers are configured to operate in response to a sub-word line driver enable signal.

13. The memory device of claim 12 ,

wherein the first sub-word line driver includes:

a first selection circuit configured to apply the selection voltage to the first word line in response to the first word line selection signal and the sub-word line driver enable signal;

a first non-selection circuit configured to apply the non-selection voltage to the first word line in response to the first word line non-selection signal; and

a second non-selection circuit configured to apply the non-selection voltage to the second word line in response to the second word line non-selection signal, and

wherein the second sub-word line driver includes:

a third non-selection circuit configured to apply the non-selection voltage to the first word line in response to the first word line non-selection signal;

a second selection circuit configured to apply the selection voltage to the second word line in response to the second word line selection signal and the sub-word line driver enable signal; and

a fourth non-selection circuit configured to apply the non-selection voltage to the second word line in response to the second word line non-selection signal.

14. The memory device of claim 13 ,

wherein the first selection circuit includes:

a first PMOS transistor connected between a first input terminal that is configured to receive the first word line selection signal and the first word line, the first PMOS transistor being configured to operate in response to the sub-word line driver enable signal;

and

a first NMOS transistor connected between the first word line and a low voltage terminal that is configured to receive the non-selection voltage, the first NMOS transistor being configured to operate in response to the sub-word line driver enable signal, and

wherein the second selection circuit includes:

a second PMOS transistor connected between a second input terminal that is configured to receive the second word line selection signal and the second word line, the second PMOS transistor being configured to operate in response to the sub-word line driver enable signal; and

a second NMOS transistor connected between the second word line and the low voltage terminal, and configured to operate in response to the sub-word line driver enable signal.

15. The memory device of claim 13 ,

wherein the first non-selection circuit includes a third NMOS transistor connected between the first word line and a low voltage terminal that is configured to receive the non-selection voltage, the third NMOS transistor being configured to operate in response to the first word line non-selection signal,

wherein the second non-selection circuit includes a fourth NMOS transistor connected between the second word line and the low voltage terminal, and configured to operate in response to the second word line non-selection signal,

wherein the third non-selection circuit includes a fifth NMOS transistor connected between the first word line and the low voltage terminal, and configured to operate in response to the first word line non-selection signal, and

wherein the fourth non-selection circuit includes a sixth NMOS transistor connected between the second word line and the low voltage terminal, and configured to operate in response to the second word line non-selection signal.

16. The memory device of claim 8 , further comprising:

a second sub-array including a plurality of third memory cells connected to a third word line and a plurality of fourth memory cells connected to a fourth word line,

wherein the second sub-word line driver is connected to the fourth word line and is further configured to apply the selection voltage to the fourth word line in response to the second word line selection signal and to apply the non-selection voltage to the fourth word line in response to the second word line non-selection signal, and

wherein the second sub-word line driver is connected to the third word line and is further configured to apply the non-selection voltage to the third word line in response to the first word line non-selection signal.

17. The memory device of claim 16 , wherein the second sub-word line driver includes:

a first non-selection circuit configured to apply the non-selection voltage to the first word line in response to the first word line non-selection signal;

a second selection circuit configured to apply the selection voltage to the second and fourth word lines in response to the second word line selection signal;

a second non-selection circuit configured to apply the non-selection voltage to the second and fourth word lines in response to the second word line non-selection signal; and

a third non-selection circuit configured to apply the non-selection voltage to the third word line in response to the first word line non-selection signal.

18. The memory device of claim 17 , wherein the first word line and the third word line are in a first row, and the second word line and the fourth word line are in a second row.

19. A memory device comprising:

a first memory cell including a storage capacitor, and a selection transistor connected between the storage capacitor and a first word line;

a first sub-word line driver connected to a first end of the first word line, and configured to apply one of a selection voltage and a non-selection voltage to the first word line in response to a first word line control signal; and

a second sub-word line driver connected to a second end of the first word line,

wherein, in response to the first word line control signal, the second sub-word line driver is configured to float the first word line or to apply the non-selection voltage to the first word line.

20. The memory device of claim 19 ,

wherein, when the first word line control signal indicates that the first word line is a selection word line, the first sub-word line driver is configured to apply the selection voltage through the first end of the first word line, and the second sub-word line driver is configured to float the second end of the first word line, and

wherein, when the first word line control signal indicates that the first word line is a non-selection word line, the first sub-word line driver is configured to apply the non-selection voltage through the first end of the first word line, and the second sub-word line driver is configured to apply the non-selection voltage through the second end of the first word line.