Package structure and fabrication methods
The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor package. In one embodiment, a glass or silicon substrate is structured by micro-blasting or laser ablation to form structures for formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor package with embedded dies therein.
1. A semiconductor device package, comprising:
a frame, comprising:
a patterned substrate comprising a semiconductor material, the patterned substrate having a first side opposite a second side;
a first opening formed in the patterned substrate and extending from the first side to the second side; and
a plurality of second openings formed in the patterned substrate along an edge of the first opening and extending from the first side to the second side, each of the plurality of second openings having a first lateral dimension adjacent the first side and a second lateral dimension adjacent the second side, wherein a morphology of the plurality of second openings is different from a morphology of the first opening;
a semiconductor device disposed within the first opening;
a metallic interconnection disposed within at least one of the plurality of second openings and extending at least between the first side and the second side;
a dielectric material disposed over the first side and the second side and within the first opening and each of the plurality of second openings, the dielectric material disposed over each side of the semiconductor device and between the metallic interconnection and a sidewall of the at least one of the plurality of second openings; and
an intermediate layer disposed between the dielectric material and the metallic interconnection within the at least one of the plurality of second openings.
2. The semiconductor device package of claim 1 , wherein the patterned substrate comprises a silicon substrate.
3. The semiconductor device package of claim 1 , wherein the dielectric material comprises an epoxy resin.
4. The semiconductor device package of claim 3 , wherein the epoxy resin comprises ceramic filler particles.
5. The semiconductor device package of claim 4 , wherein the ceramic filler particles comprise at least one of silica, aluminum nitride, aluminum oxide, silicon carbide, silicon nitride, zirconium silicate, wollastonite, beryllium oxide, cerium dioxide, boron nitride, calcium copper titanium oxide, magnesium oxide, titanium dioxide, and zinc oxide.
6. The semiconductor device package of claim 1 , wherein the intermediate layer comprises at least one of titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, molybdenum, cobalt oxide, and cobalt nitride.
7. The semiconductor device package of claim 1 , wherein the intermediate layer comprises at least one of copper, tungsten, aluminum, silver, and gold.
8. The semiconductor device package of claim 1 , wherein the intermediate layer comprises a first layer comprising molybdenum and a second layer comprising copper.
9. A semiconductor device package, comprising:
a frame, comprising:
a patterned substrate comprising a semiconductor material, the patterned substrate having a first side opposite a second side, the patterned substrate further comprising:
a first opening formed in the patterned substrate and extending from the first side to the second side; and
one or more rows of second openings formed in the patterned substrate along an edge of the first opening and extending from the first side to the second side, each second opening having a first lateral dimension adjacent the first side and a second lateral dimension adjacent the second side, wherein a morphology of the one or more rows of second openings is different from a morphology of the first opening;
a semiconductor device disposed within the first opening;
a metallic interconnection disposed within at least one of the one or more rows of second openings and extending at least between the first side and the second side;
a dielectric material disposed over the first side and the second side and within the first opening and each of the one or more rows of second openings, the dielectric material disposed over each side of the semiconductor device and between the metallic interconnection and a sidewall of the at least one of the one or more rows of second openings; and
one or more intermediate layers disposed between the dielectric material and the metallic interconnection within the at least one of the one or more rows of second openings.
10. The semiconductor device package of claim 9 , wherein the patterned substrate comprises a silicon substrate.
11. The semiconductor device package of claim 9 , wherein the dielectric material comprises a laminated epoxy resin.
12. The semiconductor device package of claim 11 , wherein the epoxy resin comprises ceramic filler particles.
13. The semiconductor device package of claim 12 , wherein the ceramic filler particles comprise at least one of silica, aluminum nitride, aluminum oxide, silicon carbide, silicon nitride, zirconium silicate, wollastonite, beryllium oxide, cerium dioxide, boron nitride, calcium copper titanium oxide, magnesium oxide, titanium dioxide, and zinc oxide.
14. The semiconductor device package of claim 12 , wherein the ceramic filler particles comprise at least one of silica, aluminum nitride, aluminum oxide, silicon carbide, silicon nitride, zirconium silicate, wollastonite, beryllium oxide, cerium dioxide, boron nitride, calcium copper titanium oxide, magnesium oxide, titanium dioxide, and zinc oxide.
15. The semiconductor device package of claim 9 , wherein the one or more intermediate layers comprise at least one of titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, molybdenum, cobalt oxide, and cobalt nitride.
16. The semiconductor device package of claim 9 , wherein the one or more intermediate layers comprise at least one of copper, tungsten, aluminum, silver, and gold.
17. The semiconductor device package of claim 15 , wherein the one or more intermediate layers further comprise at least one of copper, tungsten, aluminum, silver, and gold.
18. A semiconductor device package, comprising:
a frame, comprising:
a patterned substrate comprising a semiconductor material, the patterned substrate having a first side opposite a second side;
a first opening formed in the patterned substrate and extending from the first side to the second side; and
a second opening formed in the patterned substrate along an edge of the first opening and extending from the first side to the second side, the second opening having a first lateral dimension adjacent the first side and a second lateral dimension adjacent the second side;
a semiconductor device disposed within the first opening;
a metallic interconnection disposed within the second opening and extending at least between the first side and the second side;
a dielectric material disposed over the first side and the second side and within the first opening and the second opening, the dielectric material disposed over each side of the semiconductor device and between the metallic interconnection and a sidewall of the second opening;
a first intermediate layer disposed between the dielectric material and the patterned substrate; and
a second intermediate layer disposed between the dielectric material and the metallic interconnection within the second opening.
19. The semiconductor device package of claim 18 , wherein the dielectric material comprises a laminated epoxy resin.
20. The semiconductor device package of claim 19 , wherein the epoxy resin comprises ceramic filler particles.