Integrated dipole flow for transistor

1. An electronic device comprising:

a source region, a drain region and a channel separating the source region and drain region; and

a dipole region on a top surface of the channel, the dipole region comprising an interlayer dielectric, a high-κ dielectric material, and a dipole layer, the dipole layer deposited by atomic layer deposition (ALD) at a temperature in a range of from 200° C. to about 500° C. of alternating cycles of titanium nitride (TiN) and a dipole precursor, the dipole layer comprising one or more of titanium lanthanum nitride (TiLaN), titanium yttrium nitride (TiYN), titanium strontium nitride (TiSrN), or titanium magnesium nitride (TiMgN).

2. The electronic device of claim 1 , wherein the channel comprises n-type material and the dipole precursor comprises one or more of lanthanum nitride (LaN), yttrium nitride (YN), strontium nitride (SrN), or magnesium nitride (MgN).

3. The electronic device of claim 1 , further comprising a gate on the dipole region.

4. The electronic device of claim 1 , wherein the source region and the drain region independently comprise one or more of copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), platinum (Pt), phosphorus (P), germanium (Ge), silicon (Si), aluminum (Al), or zirconium (Zr).

5. The electronic device of claim 1 , wherein the interlayer dielectric comprises a low-κ dielectric.

6. The electronic device of claim 5 , wherein the low-κ dielectric is selected from one or more of silicon, silicon oxide, doped silicon, doped silicon oxide, or spin-on dielectrics.

7. The electronic device of claim 1 , wherein the high-κ dielectric material comprises one or more of hafnium oxide or lanthanum (La) doped high-κ dielectrics.

8. The electronic device of claim 1 , further comprising a capping layer on the dipole region, the capping layer comprising one or more of titanium nitride or titanium aluminum.

9. The electronic device of claim 1 , wherein the dipole layer has as thickness less than about 50 Å.

10. An electronic device comprising:

a source region, a drain region and a channel separating the source region and drain region;

a dipole region on a top surface of the channel, the dipole region comprising an interlayer dielectric, a high-κ dielectric material, and a dipole layer, the dipole layer deposited by atomic layer deposition (ALD) at a temperature in a range of from 200° C. to about 500° C. of alternating cycles of a hafnium precursor and a second precursor, the dipole layer comprising one or more of hafnium carbide (HfC), hafnium nitride (HfN), hafnium oxynitride (HfON), hafnium oxycarbide (HfOC), hafnium carbide aluminum (HfCAl), hafnium aluminum nitride (HfAlN), or hafnium carbonitride (HfCN);

a gate on the dipole region; and

a capping layer on the dipole region.

11. The electronic device of claim 10 , wherein the source region and the drain region independently comprise one or more of copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), platinum (Pt), phosphorus (P), germanium (Ge), silicon (Si), aluminum (Al), or zirconium (Zr).

12. The electronic device of claim 10 , wherein the interlayer dielectric comprises a low-κ dielectric.

13. The electronic device of claim 12 , wherein the low-κ dielectric is selected from one or more of silicon, silicon oxide, doped silicon, doped silicon oxide, or spin-on dielectrics.

14. The electronic device of claim 10 , wherein the high-κ dielectric material comprises one or more of hafnium oxide or lanthanum (La) doped high-κ dielectrics.

15. The electronic device of claim 10 , wherein the capping layer comprises one or more of titanium nitride or titanium aluminum.

16. The electronic device of claim 10 , wherein the dipole layer has a thickness less than about 50 Å.